公开(公告)号：US20180233567A1

公开(公告)日：2018-08-16

申请号：US15949137

申请日：2018-04-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jung-Hun Choi ,  Da-Il Eom ,  Sun-Jung Lee ,  Sung-Uk Jang

IPC: H01L29/417 ,  H01L27/092 ,  H01L29/08 ,  H01L21/8234 ,  H01L29/16 ,  H01L21/8238 ,  H01L21/768 ,  H01L23/485 ,  H01L29/165 ,  H01L29/78

CPC classification number: H01L29/41791 ,  H01L21/76805 ,  H01L21/76846 ,  H01L21/823418 ,  H01L21/823425 ,  H01L21/823431 ,  H01L21/823475 ,  H01L21/823814 ,  H01L21/823871 ,  H01L23/485 ,  H01L27/0924 ,  H01L29/0847 ,  H01L29/1604 ,  H01L29/165 ,  H01L29/41783 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785 ,  H01L2029/7858

Abstract: An integrated circuit device includes a source/drain region having a recess in its top, a contact plug extending on the source/drain region from within the recess, and a metal silicide layer lining the recess and having a first portion covering a bottom of the contact plug and a second portion that is integral with the first portion and covers a lower part of sides of the contact plug. The second portion of the silicide layer may have a thickness different from a thickness of the first portion of the silicide layer. The silicide layer is formed at a relatively low temperature to offer an improved resistance characteristic as between the source/drain region and the contact plug.

公开(公告)号：US10276675B2

公开(公告)日：2019-04-30

申请号：US15949137

申请日：2018-04-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jung-Hun Choi ,  Da-Il Eom ,  Sun-Jung Lee ,  Sung-Uk Jang

IPC: H01L29/417 ,  H01L27/092 ,  H01L29/16 ,  H01L29/165 ,  H01L21/8238 ,  H01L21/768 ,  H01L21/8234 ,  H01L23/485 ,  H01L29/78 ,  H01L29/66

Abstract: An integrated circuit device includes a source/drain region having a recess in its top, a contact plug extending on the source/drain region from within the recess, and a metal silicide layer lining the recess and having a first portion covering a bottom of the contact plug and a second portion that is integral with the first portion and covers a lower part of sides of the contact plug. The second portion of the silicide layer may have a thickness different from a thickness of the first portion of the silicide layer. The silicide layer is formed at a relatively low temperature to offer an improved resistance characteristic as between the source/drain region and the contact plug.

公开(公告)号：US09786764B2

公开(公告)日：2017-10-10

申请号：US14920267

申请日：2015-10-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chan-Jin Park ,  Chung-Hwan Shin ,  Sung-Woo Kang ,  Young-Mook Oh ,  Sun-Jung Lee ,  Jeong-Nam Han

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/768 ,  H01L21/285

CPC classification number: H01L29/66545 ,  H01L21/28518 ,  H01L21/76816 ,  H01L21/76831 ,  H01L23/485 ,  H01L29/66795 ,  H01L29/7855 ,  H01L2029/7858 ,  H01L2221/1063

Abstract: A semiconductor device includes an active fin formed to extend in a first direction, a gate formed on the active fin and extending in a second direction crossing the first direction, a source/drain formed on upper portions of the active fin and disposed at one side of the gate, an interlayer insulation layer covering the gate and the source/drain, a source/drain contact passing through the interlayer insulation layer to be connected to the source/drain and including a first contact region and a second contact region positioned between the source/drain and the first contact region, and a spacer layer formed between the first contact region and the interlayer insulation layer. A width of the second contact region in the first direction is greater than the sum of a width of the first contact region in the first direction and a width of the spacer layer in the first direction.