公开(公告)号：US20230371311A1

公开(公告)日：2023-11-16

申请号：US18355732

申请日：2023-07-20

申请人： Samsung Display Co., Ltd.

发明人： Jongjun BAEK ,  Jaewoo JEONG ,  Byungsoo SO

IPC分类号： H10K59/121 ,  H01L29/16 ,  H01L29/04 ,  H01L29/786 ,  H10K50/12 ,  H10K50/165 ,  H10K59/123 ,  H10K71/00

CPC分类号： H10K59/1213 ,  H01L29/1604 ,  H01L29/045 ,  H01L29/78675 ,  H10K50/12 ,  H10K50/165 ,  H10K59/123 ,  H10K71/00

摘要： A display apparatus includes a substrate, a first thin film transistor on the substrate, the first thin film transistor including an active layer including a source region, a drain region, and a channel region between the source region and the drain region, and a display device on the substrate and electrically connected to the first thin film transistor. The source region, the drain region, and the channel region include a first dopant and a second dopant, the second dopant being different from the first dopant. A concentration of the first dopant in the channel region is less than a concentration of the first dopant in the source region and the drain region.

公开(公告)号：US11744110B2

公开(公告)日：2023-08-29

申请号：US17317304

申请日：2021-05-11

申请人： Samsung Display Co., Ltd.

发明人： Jongjun Baek ,  Jaewoo Jeong ,  Byungsoo So

IPC分类号： H10K59/121 ,  H01L29/16 ,  H01L29/04 ,  H01L29/786 ,  H10K50/12 ,  H10K50/165 ,  H10K59/123 ,  H10K71/00

CPC分类号： H10K59/1213 ,  H01L29/045 ,  H01L29/1604 ,  H01L29/78675 ,  H10K50/12 ,  H10K50/165 ,  H10K59/123 ,  H10K71/00

摘要： A display apparatus includes a substrate, a first thin film transistor on the substrate, the first thin film transistor including an active layer including a source region, a drain region, and a channel region between the source region and the drain region, and a display device on the substrate and electrically connected to the first thin film transistor. The source region, the drain region, and the channel region include a first dopant and a second dopant, the second dopant being different from the first dopant. A concentration of the first dopant in the channel region is less than a concentration of the first dopant in the source region and the drain region.

公开(公告)号：US09799731B2

公开(公告)日：2017-10-24

申请号：US15004872

申请日：2016-01-22

申请人： Ideal Power Inc.

发明人： William C. Alexander

IPC分类号： H01L29/747 ,  H01L29/10 ,  H01L29/417 ,  H01L29/423 ,  H01L29/73 ,  H01L29/732 ,  H01L29/737 ,  H01L29/739 ,  H01L29/06 ,  H01L29/08 ,  H01L29/16 ,  H02M3/158 ,  H03K17/60 ,  H03K17/66 ,  H02M7/487

CPC分类号： H01L29/1004 ,  H01L29/0619 ,  H01L29/0804 ,  H01L29/0817 ,  H01L29/0821 ,  H01L29/16 ,  H01L29/1604 ,  H01L29/41708 ,  H01L29/42304 ,  H01L29/73 ,  H01L29/732 ,  H01L29/7375 ,  H01L29/7393 ,  H01L29/7395 ,  H01L29/747 ,  H02M3/1582 ,  H02M7/487 ,  H03K17/60 ,  H03K17/66

摘要： Power is inverted using double-base-contact bidirectional bipolar transistors in a three-level-inverter topology. The transistors not only switch to synthesize a PWM approximation of the desired AC waveform, but also have transient phases of diode conduction before each full turn-on or turn-off.

公开(公告)号：US09741871B2

公开(公告)日：2017-08-22

申请号：US14931307

申请日：2015-11-03

申请人： International Business Machines Corporation

发明人： Bahman Hekmatshoartabari ,  Ghavam G. Shahidi ,  Yanning Sun

IPC分类号： H01L29/808 ,  H01L29/423 ,  H01L29/06 ,  H01L29/66 ,  H01L21/283 ,  H01L29/417 ,  H01L27/12 ,  H01L29/04 ,  H01L29/10

CPC分类号： H01L29/802 ,  H01L21/283 ,  H01L27/12 ,  H01L29/04 ,  H01L29/0649 ,  H01L29/0843 ,  H01L29/1054 ,  H01L29/1066 ,  H01L29/1604 ,  H01L29/165 ,  H01L29/41775 ,  H01L29/42356 ,  H01L29/456 ,  H01L29/66901 ,  H01L29/66916 ,  H01L29/8086

摘要： A junction field effect transistor (JFET) comprises an insulating carrier substrate, a base semiconductor substrate formed on the insulating carrier substrate and a gate region formed on the base semiconductor substrate. The gate region forms a junction with the base semiconductor substrate. The JFET further comprises a first source/drain region formed on the base semiconductor substrate and located on a first side of the gate region and a second source/drain region formed on the base semiconductor substrate and located on a second side of the gate region. A gate stack is deposited on the gate region, a first source/drain stack is deposited on the first source/drain region and a second source/drain stack is deposited on the second source/drain region. At least one of the gate stack, first source/drain stack and second source/drain stack overlaps onto another one of the gate stack, first source/drain stack and second source/drain stack.

公开(公告)号：US09728642B2

公开(公告)日：2017-08-08

申请号：US14932112

申请日：2015-11-04

申请人： International Business Machines Corporation

发明人： Bruce B. Doris ,  Gauri Karve ,  Fee Li Lie ,  Junli Wang

IPC分类号： H01L29/78 ,  H01L29/66 ,  H01L29/10 ,  H01L21/308 ,  H01L29/16 ,  H01L29/161

CPC分类号： H01L29/7848 ,  H01L21/3065 ,  H01L21/308 ,  H01L29/0649 ,  H01L29/1054 ,  H01L29/1604 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/7842 ,  H01L29/785

摘要： A method for fabricating a semiconductor device comprises patterning a strained fin from a strained layer of semiconductor material arranged on a substrate, depositing a first layer of semiconductor material on the fin and exposed portions of the substrate, patterning and etching to remove a portion of the first layer of semiconductor material and a portion of the fin to expose a portion of the substrate, depositing a second layer of semiconductor material on exposed portions of the substrate and the first layer of semiconductor material, and patterning and etching to remove a portion of the second layer of semiconductor material layer and the first layer of semiconductor material to define a dummy gate stack, the dummy gate stack is operative to substantially maintain the strain in the strained fin.

公开(公告)号：US20170125590A1

公开(公告)日：2017-05-04

申请号：US15344888

申请日：2016-11-07

申请人： International Business Machines Corporation

发明人： Bruce B. Doris ,  Gauri Karve ,  Fee Li Lie ,  Junli Wang

IPC分类号： H01L29/78 ,  H01L21/3065 ,  H01L29/06 ,  H01L29/66 ,  H01L29/165

CPC分类号： H01L29/7848 ,  H01L21/3065 ,  H01L21/308 ,  H01L29/0649 ,  H01L29/1054 ,  H01L29/1604 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/7842 ,  H01L29/785

摘要： A method for fabricating a semiconductor device comprises patterning a strained fin from a strained layer of semiconductor material arranged on a substrate, depositing a first layer of semiconductor material on the fin and exposed portions of the substrate, patterning and etching to remove a portion of the first layer of semiconductor material and a portion of the fin to expose a portion of the substrate, depositing a second layer of semiconductor material on exposed portions of the substrate and the first layer of semiconductor material, and patterning and etching to remove a portion of the second layer of semiconductor material layer and the first layer of semiconductor material to define a dummy gate stack, the dummy gate stack is operative to substantially maintain the strain in the strained fin.

公开(公告)号：US09559110B2

公开(公告)日：2017-01-31

申请号：US14856131

申请日：2015-09-16

申请人： SANDISK 3D LLC

发明人： Thomas H. Lee

IPC分类号： H01L29/00 ,  H01L27/115 ,  G11C16/34 ,  H01L21/822 ,  H01L27/06 ,  H01L27/112 ,  H01L29/423 ,  H01L29/66 ,  H01L29/788 ,  H01L29/792 ,  H01L29/861 ,  H01L29/16 ,  G11C16/10 ,  G11C16/14 ,  G11C16/26 ,  H01L29/06 ,  H01L29/51 ,  H01L27/12

CPC分类号： H01L27/11582 ,  G11C16/0466 ,  G11C16/10 ,  G11C16/14 ,  G11C16/26 ,  G11C16/3427 ,  G11C2211/5612 ,  H01L21/31053 ,  H01L21/76819 ,  H01L21/8221 ,  H01L23/528 ,  H01L23/5329 ,  H01L27/0688 ,  H01L27/112 ,  H01L27/11286 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11558 ,  H01L27/11565 ,  H01L27/11568 ,  H01L27/11573 ,  H01L27/11578 ,  H01L27/1158 ,  H01L27/12 ,  H01L27/1203 ,  H01L29/0626 ,  H01L29/0661 ,  H01L29/16 ,  H01L29/1604 ,  H01L29/42324 ,  H01L29/42332 ,  H01L29/42364 ,  H01L29/511 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7391 ,  H01L29/78642 ,  H01L29/7881 ,  H01L29/7889 ,  H01L29/792 ,  H01L29/7926 ,  H01L29/861 ,  H01L29/8616

摘要： There is provided a monolithic three dimensional array of charge storage devices which includes a plurality of device levels, wherein at least one surface between two successive levels is planarized by chemical mechanical polishing.

摘要翻译： 提供了一种包含多个器件级的电荷存储器件的单片三维阵列，其中通过化学机械抛光将两个连续级之间的至少一个表面平坦化。

公开(公告)号：US20160359023A1

公开(公告)日：2016-12-08

申请号：US15237260

申请日：2016-08-15

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Stephen W. Bedell ,  Joel P. De Souza ,  Jeehwan Kim ,  Devendra K. Sadana

IPC分类号： H01L29/66 ,  H01L21/288 ,  H01L21/02 ,  H01L21/24 ,  H01L29/10 ,  H01L29/78

CPC分类号： H01L29/66795 ,  H01L21/0245 ,  H01L21/02488 ,  H01L21/02502 ,  H01L21/02513 ,  H01L21/02532 ,  H01L21/02592 ,  H01L21/228 ,  H01L21/24 ,  H01L21/26513 ,  H01L21/288 ,  H01L21/324 ,  H01L21/7624 ,  H01L21/76251 ,  H01L21/76283 ,  H01L29/1054 ,  H01L29/1604 ,  H01L29/161 ,  H01L29/775 ,  H01L29/7842 ,  H01L29/785 ,  H01L29/78684 ,  H01L29/78696

摘要： A layer of amorphous silicon is formed on a germanium-on-insulator substrate, or a layer of germanium is formed on a silicon-on-insulator substrate. An anneal is then performed which causes thermal mixing of silicon and germanium atoms within one of the aforementioned structures and subsequent formation of a silicon germanium-on-insulator material.

公开(公告)号：US20160351413A1

公开(公告)日：2016-12-01

申请号：US14724947

申请日：2015-05-29

申请人： Infineon Technologies AG

发明人： Gerhard SCHMIDT ,  Markus KAHN ,  Christian MAIER ,  Philipp KOCH ,  Juergen STEINBRENNER

IPC分类号： H01L21/311 ,  H01L21/02 ,  H01L21/3065

CPC分类号： H01L21/02115 ,  H01L21/02046 ,  H01L21/02164 ,  H01L21/02301 ,  H01L21/02315 ,  H01L21/28194 ,  H01L21/3065 ,  H01L29/0615 ,  H01L29/0619 ,  H01L29/0638 ,  H01L29/1602 ,  H01L29/1604 ,  H01L29/51 ,  H01L29/66181 ,  H01L29/7395

摘要： According to various embodiments, a method for processing a semiconductor layer may include: generating an etch plasma in a plasma chamber of a remote plasma source, wherein the plasma chamber of the remote plasma source is coupled to a processing chamber for processing the semiconductor layer; introducing the etch plasma into the processing chamber to remove a native oxide layer from a surface of the semiconductor layer and at most a negligible amount of semiconductor material of the semiconductor layer; and, subsequently, depositing a dielectric layer directly on the surface of the semiconductor layer.

摘要翻译： 根据各种实施例，用于处理半导体层的方法可以包括：在远程等离子体源的等离子体室中产生蚀刻等离子体，其中远程等离子体源的等离子体室耦合到用于处理半导体层的处理室; 将蚀刻等离子体引入处理室以从半导体层的表面去除自然氧化物层，并且至多可忽略量的半导体层的半导体材料; 并且随后将电介质层直接沉积在半导体层的表面上。

公开(公告)号：US20160351399A1

公开(公告)日：2016-12-01

申请号：US15164358

申请日：2016-05-25

申请人： Ideal Power Inc.

发明人： Richard A. Blanchard ,  William C. Alexander

IPC分类号： H01L21/265 ,  H01L21/283 ,  H01L21/306 ,  H01L21/324 ,  H01L21/683 ,  H01L29/739 ,  H01L29/66 ,  H01L21/18 ,  H01L21/78

CPC分类号： H01L21/265 ,  H01L21/187 ,  H01L21/2252 ,  H01L21/283 ,  H01L21/304 ,  H01L21/30625 ,  H01L21/324 ,  H01L21/6835 ,  H01L21/6836 ,  H01L21/78 ,  H01L29/0619 ,  H01L29/0821 ,  H01L29/1604 ,  H01L29/4236 ,  H01L29/66348 ,  H01L29/732 ,  H01L29/7375 ,  H01L29/7397 ,  H01L2221/68304 ,  H01L2221/68327 ,  H03K17/66

摘要： Methods and systems for double-sided semiconductor device fabrication. Devices having multiple leads on each surface can be fabricated using a high-temperature-resistant handle wafer and a medium-temperature-resistant handle wafer. Dopants can be introduced on both sides shortly before a single long high-temperature diffusion step diffuses all dopants to approximately equal depths on both sides. All high-temperature processing occurs with no handle wafer or with a high-temperature handle wafer attached. Once a medium-temperature handle wafer is attached, no high-temperature processing steps occur. High temperatures can be considered to be those which can result in damage to the device in the presence of aluminum-based metallizations.

摘要翻译： 双面半导体器件制造的方法和系统。 在每个表面上具有多个引线的器件可以使用耐高温处理晶片和中温耐用的晶片来制造。 在单个长的高温扩散步骤之前不久可以在两侧引入掺杂剂，将所有掺杂剂扩散到两侧的大致相等的深度。 所有的高温处理都是在没有处理晶片的情况下进行的，或者附着有高温处理晶片。 一旦安装了中温处理晶片，则不会发生高温处理步骤。 可以认为高温可能是在存在铝基金属化时可能导致器件损坏的那些。