公开(公告)号：US08796107B2

公开(公告)日：2014-08-05

申请号：US13679345

申请日：2012-11-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kevin Ahn ,  Bo-Un Yoon ,  Jeong-Nam Han

IPC: H01L21/762 ,  H01L21/311 ,  H01L21/336 ,  H01L21/02 ,  H01L21/306 ,  H01L29/66 ,  H01L21/04

CPC classification number: H01L21/76229 ,  H01L21/0206 ,  H01L21/02065 ,  H01L21/0475 ,  H01L21/30604 ,  H01L21/30621 ,  H01L21/31055 ,  H01L21/31056 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/76205 ,  H01L21/823468 ,  H01L21/823481 ,  H01L29/66545

Abstract: Provided are methods for fabricating a semiconductor device. The methods include forming a hard mask pattern on a semiconductor substrate, forming a first trench having a first width and a second trench having a second width on the semiconductor substrate using the hard mask pattern as a mask, forming an oxide film on the hard mask pattern and the first and second trenches, forming first and second isolation films on the first and second trenches by planarizing the oxide film until the hard mask pattern is exposed, and etching the first isolation film by a first thickness by performing dry cleaning on the semiconductor substrate and etching the second isolation film by a second thickness different from the first thickness.

Abstract translation: 提供了制造半导体器件的方法。 所述方法包括在半导体衬底上形成硬掩模图案，使用硬掩模图案作为掩模，在半导体衬底上形成具有第一宽度的第一沟槽和具有第二宽度的第二沟槽，在硬掩模上形成氧化物膜 图案和第一沟槽和第二沟槽，通过平坦化氧化膜直到硬掩模图案露出来在第一和第二沟槽上形成第一和第二隔离膜，并且通过对半导体进行干洗来蚀刻第一隔离膜第一厚度第一厚度 衬底并用不同于第一厚度的第二厚度蚀刻第二隔离膜。

公开(公告)号：US10192973B2

公开(公告)日：2019-01-29

申请号：US15239200

申请日：2016-08-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang-Jine Park ,  Bo-Un Yoon ,  Ha-Young Jeon ,  Byung-Kwon Cho ,  Jeong-Nam Han

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/28 ,  H01L29/49 ,  H01L27/088 ,  H01L29/423

Abstract: A semiconductor device includes a gate spacer defining a trench. The trench includes a first part and a second part sequentially positioned on a substrate. An inner surface of the first part has a slope of an acute angle and an inner surface of the second part has a slope of a right angle or obtuse angle with respect to the substrate. A gate electrode fills at least a portion of the trench.

公开(公告)号：US20140206169A1

公开(公告)日：2014-07-24

申请号：US13834118

申请日：2013-03-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ji Hoon Cha ,  Jae-Jik Baek ,  Bo-Un Yoon ,  Young-Sang Youn ,  Jeong-Nam Han

IPC: H01L29/66

CPC classification number: H01L29/66628 ,  H01L21/30604 ,  H01L21/3065 ,  H01L21/3086 ,  H01L21/76229 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823481 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823878 ,  H01L29/66636 ,  H01L29/7848

Abstract: A method of forming a semiconductor device can include providing a plasma nitrided exposed top surface including an active region and an isolation region. The exposed top surface including the active region and the isolation region can be subjected to etching to form a deeper recess in the active region that in the isolation region and an unmerged epitaxial stress film can be grown in the deeper recess.

Abstract translation: 形成半导体器件的方法可以包括提供包括有源区和隔离区的等离子体氮化的暴露顶表面。 包括有源区和隔离区的暴露的顶表面可以进行蚀刻，以在有源区中形成更深的凹槽，在隔离区中形成较深的凹槽，并且在较深的凹槽中可以生长未熔合的外延应力膜。

公开(公告)号：US09786764B2

公开(公告)日：2017-10-10

申请号：US14920267

申请日：2015-10-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chan-Jin Park ,  Chung-Hwan Shin ,  Sung-Woo Kang ,  Young-Mook Oh ,  Sun-Jung Lee ,  Jeong-Nam Han

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/768 ,  H01L21/285

CPC classification number: H01L29/66545 ,  H01L21/28518 ,  H01L21/76816 ,  H01L21/76831 ,  H01L23/485 ,  H01L29/66795 ,  H01L29/7855 ,  H01L2029/7858 ,  H01L2221/1063

Abstract: A semiconductor device includes an active fin formed to extend in a first direction, a gate formed on the active fin and extending in a second direction crossing the first direction, a source/drain formed on upper portions of the active fin and disposed at one side of the gate, an interlayer insulation layer covering the gate and the source/drain, a source/drain contact passing through the interlayer insulation layer to be connected to the source/drain and including a first contact region and a second contact region positioned between the source/drain and the first contact region, and a spacer layer formed between the first contact region and the interlayer insulation layer. A width of the second contact region in the first direction is greater than the sum of a width of the first contact region in the first direction and a width of the spacer layer in the first direction.

公开(公告)号：US10821572B2

公开(公告)日：2020-11-03

申请号：US15926244

申请日：2018-03-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Suk-Hoon Jeong ,  Sang-Hak Lee ,  Geun-Kyu Choi ,  Chang-Sun Hwang ,  Tae-Young Kwon ,  Young-Sang Kim ,  Hyung-Kyu Jin ,  Jeong-Nam Han

IPC: B24B37/00 ,  B24B37/015 ,  B24B55/02 ,  B24B49/14 ,  B24B37/26

Abstract: A method of controlling a chemical mechanical polishing (CMP) process, a temperature control, and a CMP apparatus, the method including measuring actual temperatures of at least two regions in a platen in real time during the CMP process in which a polishing pad attached to the platen polishes a substrate held by a polishing head using slurry and deionized water; receiving the measured actual temperatures of the regions; and individually controlling the actual temperatures of the regions in real time during the CMP process to provide the regions with a predetermined set CMP process temperature.

公开(公告)号：US09466697B2

公开(公告)日：2016-10-11

申请号：US14721004

申请日：2015-05-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang-Jine Park ,  Bo-Un Yoon ,  Jeong-Nam Han ,  Myung-Geun Song

IPC: H01L29/66 ,  H01L21/285 ,  H01L21/768 ,  H01L29/417 ,  H01L29/78 ,  H01L29/49

CPC classification number: H01L29/66636 ,  H01L21/28518 ,  H01L21/76802 ,  H01L29/4175 ,  H01L29/41775 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/7834 ,  H01L29/7845 ,  H01L29/7848

Abstract: Provided are a semiconductor device, which can facilitate a salicide process and can prevent a gate from being damaged due to misalign, and a method of manufacturing of the semiconductor device. The method includes forming a first insulation layer pattern on a substrate having a gate pattern and a source/drain region formed at both sides of the gate pattern, the first insulation layer pattern having an exposed portion of the source/drain region, forming a silicide layer on the exposed source/drain region, forming a second insulation layer on the entire surface of the substrate to cover the first insulation layer pattern and the silicide layer, and forming a contact hole in the second insulation layer to expose the silicide layer.

Abstract translation: 提供一种可以促进自对准硅化物工艺并且可以防止栅极由于不对准而被损坏的半导体器件，以及半导体器件的制造方法。 该方法包括在具有形成在栅极图案的两侧的栅极图案和源极/漏极区域的衬底上形成第一绝缘层图案，第一绝缘层图案具有源极/漏极区域的暴露部分，形成硅化物 在所述暴露的源极/漏极区上形成第二绝缘层，以在所述衬底的整个表面上形成覆盖所述第一绝缘层图案和所述硅化物层的第二绝缘层，以及在所述第二绝缘层中形成接触孔以露出所述硅化物层。

公开(公告)号：US09040415B2

公开(公告)日：2015-05-26

申请号：US14286108

申请日：2014-05-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang-Jine Park ,  Bo-Un Yoon ,  Young-Sang Youn ,  Jeong-Nam Han ,  Kee-Sang Kwon ,  Doo-Sung Yun ,  Byung-Kwon Cho ,  Ji-Hoon Cha

IPC: H01L21/4763 ,  H01L29/66

CPC classification number: H01L29/66477 ,  H01L21/02063 ,  H01L21/31116 ,  H01L21/76804 ,  H01L21/76814 ,  H01L21/76826 ,  H01L21/76897 ,  H01L29/41791 ,  H01L29/66553 ,  H01L29/66795 ,  H01L2221/1063

Abstract: A method for forming a trench includes etching an oxide layer to form a trench therein, conformally forming a first reaction layer along a surface of the trench, the first reaction layer including a first region on an upper portion of the trench and a second region on a lower portion of the trench, forming a barrier layer by reacting a first amount of etching gas with the first region of the first reaction layer, and etching the oxide layer on a lower portion of the second region by reacting a second amount of etching gas with the second region of the first reaction layer, the second amount of etching gas being greater than the first amount of etching gas.

Abstract translation: 一种用于形成沟槽的方法包括蚀刻氧化物层以在其中形成沟槽，沿着沟槽的表面共形形成第一反应层，第一反应层包括沟槽上部的第一区域和第二区域 沟槽的下部，通过使第一量的蚀刻气体与第一反应层的第一区域反应形成阻挡层，并且通过使第二量的蚀刻气体反应来蚀刻第二区域的下部的氧化物层 与第一反应层的第二区域相比，第二量的蚀刻气体大于第一量的蚀刻气体。

公开(公告)号：US20140322881A1

公开(公告)日：2014-10-30

申请号：US14326760

申请日：2014-07-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang-Jine Park ,  Bo-Un Yoon ,  Jeong-Nam Han ,  Myung-Geun Song

IPC: H01L29/66

CPC classification number: H01L29/66636 ,  H01L21/28518 ,  H01L21/76802 ,  H01L29/4175 ,  H01L29/41775 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/7834 ,  H01L29/7845 ,  H01L29/7848

Abstract: Provided are a semiconductor device, which can facilitate a salicide process and can prevent a gate from being damaged due to misalign, and a method of manufacturing of the semiconductor device. The method includes forming a first insulation layer pattern on a substrate having a gate pattern and a source/drain region formed at both sides of the gate pattern, the first insulation layer pattern having an exposed portion of the source/drain region, forming a silicide layer on the exposed source/drain region, forming a second insulation layer on the entire surface of the substrate to cover the first insulation layer pattern and the silicide layer, and forming a contact hole in the second insulation layer to expose the silicide layer.

Abstract translation: 提供一种可以促进自对准硅化物工艺并且可以防止栅极由于不对准而被损坏的半导体器件，以及半导体器件的制造方法。 该方法包括在具有形成在栅极图案的两侧的栅极图案和源极/漏极区域的衬底上形成第一绝缘层图案，第一绝缘层图案具有源极/漏极区域的暴露部分，形成硅化物 在所述暴露的源极/漏极区上形成第二绝缘层，以在所述衬底的整个表面上形成覆盖所述第一绝缘层图案和所述硅化物层的第二绝缘层，以及在所述第二绝缘层中形成接触孔以露出所述硅化物层。

公开(公告)号：US10297474B2

公开(公告)日：2019-05-21

申请号：US14183994

申请日：2014-02-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang-Jine Park ,  Bo-Un Yoon ,  Jeong-Nam Han ,  Kee-Sang Kwon ,  Doo-Sung Yun ,  Won-Sang Choi

IPC: H01L21/67

Abstract: A chemical supplier includes a chemical reservoir containing a chemical mixture at a room temperature, an inner space of the chemical reservoir being separated from surroundings, a supply line through which the chemical mixture is supplied to a process chamber from the chemical reservoir, an inline heater positioned on the supply line and heating the chemical mixture in the supply line to a process temperature, and a power source driving the chemical mixture to move the chemical mixture toward the process chamber.

公开(公告)号：US09136135B2

公开(公告)日：2015-09-15

申请号：US13944087

申请日：2013-07-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae-Jik Baek ,  Ji-Hoon Cha ,  Bo-Un Yoon ,  Kwang-Wook Lee ,  Jeong-Nam Han

IPC: H01L21/306 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L21/30604 ,  H01L21/30608 ,  H01L21/823412 ,  H01L21/823425 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/66628 ,  H01L29/7833 ,  H01L29/7848

Abstract: A method of fabricating a semiconductor device includes forming a gate pattern on a substrate, and etching sides of the gate pattern using a first wet-etching process to form a first recess. The first wet-etching process includes using an etchant containing a first chemical substance including a hydroxyl functional group (—OH) and a second chemical substance capable of oxidizing the substrate. The concentration of the second chemical substance is 1.5 times or less the concentration of the first chemical substance.

Abstract translation: 制造半导体器件的方法包括在衬底上形成栅极图案，并且使用第一湿蚀刻工艺蚀刻栅极图案的侧面以形成第一凹部。 第一湿蚀刻工艺包括使用含有包含羟基官能团（-OH）的第一化学物质和能够氧化底物的第二化学物质的蚀刻剂。 第二化学物质的浓度为第一化学物质浓度的1.5倍以下。