Abstract:
An image sensor including a comparator configured to generate a comparison signal by comparing a ramp signal and a pixel signal with each other, a counter configured to generate a digital pixel value by counting an input clock signal according to the comparison signal, and a divider configured to control a frequency of the input clock signal according to an analog gain of the image sensor.
Abstract:
An image sensor includes a pixel array and N analog-to-digital converters (ADCs). The pixel array includes N pixels arranged in each of a plurality of rows, and each of the N pixels include M photoelectric conversion elements. At least one of the N ADCs are shared by at least one of the M photoelectric conversion elements included in each of the N pixels.
Abstract:
In one embodiment, an image sensor includes a pixel array including a plurality of pixels, an analog-to-digital converter configured to convert analog pixel signals output from the pixels into digital signals, a first cluster configured to store a first group of digital signals among the digital signals and to output first image data, a second cluster configured to store a second group of digital signals among the digital signals and to output second image data, and at least one cluster switch connected to the first cluster and the second cluster, a first channel, and a second channel. The image sensor is configured to transmit at least one among the first image data and the second image data to at least one among the first channel and the second channel based on an operation mode.
Abstract:
An image sensor includes a comparator configured to compare a pixel signal with a ramp signal and generate a comparison signal and a counter configured to be reset by a counter reset value based on an offset of the comparator and to generate a digital pixel signal according to the comparison signal.
Abstract:
An image sensor includes a first column pair and a second column pair among a plurality of columns of a pixel array, an analog-to-digital converter pair, and a switch arrangement circuit configured to connect the first column pair with the analog-to-digital converter pair in response to first switch control signals such that two rows among a plurality of rows in the pixel array are read during a single access time.