摘要:
An image sensor includes a first unit pixel including a first sub-pixel and a second sub-pixel, a second unit pixel including a third sub-pixel and a fourth sub-pixel, a timing controller configured to apply a first effective integration time to the first sub-pixel and the fourth sub-pixel, such that a first sensing signal and a fourth sensing signal are generated from the first sub-pixel and the fourth sub-pixel, respectively, and to apply a second effective integration time shorter than the first effective integration time to the second sub-pixel and the third sub-pixel, such that a second sensing signal and a third sensing signal are generated from the second sub-pixel and the third sub-pixel, respectively, and an analog-to-digital converter configured to perform an averaging operation on the first sensing signal and the fourth sensing signal or on the second sensing signal and the third sensing signal.
摘要:
An image sensor includes a first unit pixel including a first sub-pixel and a second sub-pixel, a second unit pixel including a third sub-pixel and a fourth sub-pixel, a timing controller configured to apply a first effective integration time to the first sub-pixel and the fourth sub-pixel, such that a first sensing signal and a fourth sensing signal are generated from the first sub-pixel and the fourth sub-pixel, respectively, and to apply a second effective integration time shorter than the first effective integration time to the second sub-pixel and the third sub-pixel, such that a second sensing signal and a third sensing signal are generated from the second sub-pixel and the third sub-pixel, respectively, and an analog-to-digital converter configured to perform an averaging operation on the first sensing signal and the fourth sensing signal or on the second sensing signal and the third sensing signal.
摘要:
A clock and data recovery circuit in accordance with an embodiment of the inventive concept includes a phase locked loop configured to receive a data stream into which an additional bit is inserted at every reference period to generate parallelized data and a clock signal, and a first detector circuit configured to determine whether the parallelized data is locked based on a bit-conversion of the data stream according to an insertion of the additional bit. The bit-conversion is executed with respect to the additional bits according to a predetermined protocol, or is executed with respect to at least one bit from among data of the data stream between a current one of the additional bits and a next one of the additional bits.
摘要:
An image sensor includes a first column pair and a second column pair among a plurality of columns of a pixel array, an analog-to-digital converter pair, and a switch arrangement circuit configured to connect the first column pair with the analog-to-digital converter pair in response to first switch control signals such that two rows among a plurality of rows in the pixel array are read during a single access time.
摘要:
An electronic device includes a pixel array that outputs a raw image including color pixels and specific pixels, a logic circuit that outputs a first binned image by performing first binning on pixels in a row direction for each unit kernel of the raw image, and a processor that outputs a second binned image by performing second binning on the first binned image. When a unit kernel includes at least one of the specific pixels, a column to which the at least one specific pixel belongs is read out at a readout timing different from a readout timing of a column to which none of the specific pixels belong and undergoes the first binning. The second binning combines a third binned image of the column to which none of the specific pixels belong with a fourth binned image of the column to which the at least one specific pixel belongs.
摘要:
An analog-to-digital converter includes a gain amplification unit configured to receive a pixel signal at a first node and to amplify a gain of the pixel signal, a first capacitor connected between the first node and a second node, an amplifier configured to receive and amplify a signal output from the gain amplification unit and the first capacitor, and a conversion circuit configured to convert an output signal of the amplifier to a digital signal based on a reference signal and output the digital signal as a first output signal.
摘要:
A programmable gain amplifier includes a sampling circuit, a source follower, a first capacitor and an error amplifier. The sampling circuit is configured to perform correlated double sampling on an input signal using a reference voltage. The first capacitor is connected between the sampling circuit and the source follower. The error amplifier is connected between an input terminal of the source follower and an output terminal of the source follower. The error amplifier is configured to reset a voltage of the output terminal of the source follower to the reference voltage during a source follower reset operation.