公开(公告)号：US20160204277A1

公开(公告)日：2016-07-14

申请号：US15075888

申请日：2016-03-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jung-Gil YANG ,  Sang-Su KIM ,  Sung-Gi HUR

IPC: H01L29/786 ,  H01L21/02 ,  H01L29/66 ,  H01L29/06 ,  H01L29/423

CPC classification number: H01L29/0673 ,  H01L21/02233 ,  H01L21/823412 ,  H01L27/088 ,  H01L27/092 ,  H01L29/0642 ,  H01L29/0676 ,  H01L29/068 ,  H01L29/0847 ,  H01L29/16 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/20 ,  H01L29/267 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66742 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/78684 ,  H01L29/78696

Abstract: A semiconductor device includes at least one nanowire that is disposed over a substrate, extends to be spaced apart from the substrate, and includes a channel region, a gate that surrounds at least a part of the channel region, and a gate dielectric film that is disposed between the channel region and the gate. A source/drain region that contacts one end of the at least one nanowire is formed in a semiconductor layer that extends from the substrate to the one end of the at least one nanowire. Insulating spacers are formed between the substrate and the at least one nanowire. The insulating spacers are disposed between the gate and the source/drain region and are formed of a material that is different from a material of the gate dielectric film.

公开(公告)号：US20170047402A1

公开(公告)日：2017-02-16

申请号：US15339690

申请日：2016-10-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jung-Gil YANG ,  Sang-Su KIM ,  Sung-Gi HUR

IPC: H01L29/06 ,  H01L29/08 ,  H01L29/161 ,  H01L29/66 ,  H01L29/20 ,  H01L27/088 ,  H01L29/786 ,  H01L29/423 ,  H01L29/16

CPC classification number: H01L29/0673 ,  H01L21/02233 ,  H01L21/823412 ,  H01L27/088 ,  H01L27/092 ,  H01L29/0642 ,  H01L29/0676 ,  H01L29/068 ,  H01L29/0847 ,  H01L29/16 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/20 ,  H01L29/267 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66742 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/78684 ,  H01L29/78696

Abstract: A semiconductor device includes at least one nanowire that is disposed over a substrate, extends to be spaced apart from the substrate, and includes a channel region, a gate that surrounds at least a part of the channel region, and a gate dielectric film that is disposed between the channel region and the gate. A source/drain region that contacts one end of the at least one nanowire is formed in a semiconductor layer that extends from the substrate to the one end of the at least one nanowire. Insulating spacers are formed between the substrate and the at least one nanowire. The insulating spacers are disposed between the gate and the source/drain region and are formed of a material that is different from a material of the gate dielectric film.

Abstract translation: 半导体器件包括至少一个纳米线，其被布置在衬底上，延伸成与衬底间隔开，并且包括通道区域，围绕沟道区域的至少一部分的栅极和栅极电介质膜，栅极电介质膜是 设置在通道区域和栅极之间。 接触至少一个纳米线的一端的源/漏区形成在从衬底延伸到至少一个纳米线的一端的半导体层中。 在衬底和至少一个纳米线之间形成绝缘间隔物。 绝缘垫片设置在栅极和源极/漏极区域之间，并且由与栅极电介质膜的材料不同的材料形成。

公开(公告)号：US20150090958A1

公开(公告)日：2015-04-02

申请号：US14489418

申请日：2014-09-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jung-Gil YANG ,  Sang-Su KIM ,  Sung-Gi HUR

IPC: H01L27/088 ,  H01L29/267 ,  H01L29/78 ,  H01L29/06 ,  H01L29/20

CPC classification number: H01L29/0673 ,  H01L21/02233 ,  H01L21/823412 ,  H01L27/088 ,  H01L27/092 ,  H01L29/0642 ,  H01L29/0676 ,  H01L29/068 ,  H01L29/0847 ,  H01L29/16 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/20 ,  H01L29/267 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66742 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/78684 ,  H01L29/78696

Abstract: A semiconductor device includes at least one nanowire that is disposed over a substrate, extends to be spaced apart from the substrate, and includes a channel region, a gate that surrounds at least a part of the channel region, and a gate dielectric film that is disposed between the channel region and the gate. A source/drain region that contacts one end of the at least one nanowire is formed in a semiconductor layer that extends from the substrate to the one end of the at least one nanowire. Insulating spacers are formed between the substrate and the at least one nanowire. The insulating spacers are disposed between the gate and the source/drain region and are formed of a material that is different from a material of the gate dielectric film.

Abstract translation: 半导体器件包括至少一个纳米线，其被布置在衬底上，延伸成与衬底间隔开，并且包括通道区域，围绕沟道区域的至少一部分的栅极和栅极电介质膜，栅极电介质膜是 设置在通道区域和栅极之间。 接触至少一个纳米线的一端的源/漏区形成在从衬底延伸到至少一个纳米线的一端的半导体层中。 在衬底和至少一个纳米线之间形成绝缘间隔物。 绝缘垫片设置在栅极和源极/漏极区域之间，并且由与栅极电介质膜的材料不同的材料形成。

公开(公告)号：US20140209976A1

公开(公告)日：2014-07-31

申请号：US14163972

申请日：2014-01-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Chang-Jae Yang ,  Sang-Su KIM ,  Jung-Dal CHOI ,  Sung-Gi HUR

IPC: H01L29/78 ,  H01L29/10

CPC classification number: H01L29/1054 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66575 ,  H01L29/66651 ,  H01L29/66795 ,  H01L29/785

Abstract: A transistor and a method of manufacturing the same are disclosed. The transistor includes a first epitaxial layer, a channel layer, a gate structure and an impurity region. The first epitaxial layer on a substrate includes a silicon-germanium-tin (SixGe1-x-ySny) single crystal having a lattice constant greater than a lattice constant of a germanium (Ge) single crystal. The channel layer is disposed adjacent to the first epitaxial layer. The channel layer includes the germanium single crystal. The gate structure is disposed on the channel layer. The impurity region is disposed at an upper portion of the channel layer adjacent to the gate structure.

Abstract translation: 公开了晶体管及其制造方法。 晶体管包括第一外延层，沟道层，栅极结构和杂质区。 衬底上的第一外延层包括具有大于锗（Ge）单晶的晶格常数的晶格常数的硅 - 锗 - 锡（SixGe1-x-ySny）单晶。 沟道层设置成与第一外延层相邻。 沟道层包括锗单晶。 栅极结构设置在沟道层上。 杂质区设置在与栅极结构相邻的沟道层的上部。