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    TUNNELING FIELD EFFECT TRANSISTOR
    3.
    发明申请
    TUNNELING FIELD EFFECT TRANSISTOR 审中-公开
    隧道场效应晶体管

    公开(公告)号：US20150200289A1

    公开(公告)日：2015-07-16

    申请号：US14570331

    申请日：2014-12-15

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Xin-Gui ZHANG ,  Tae-Yong KWON ,  Jung-Gil YANG ,  Sang-Su KIM

    IPC: H01L29/78 ,  H01L29/205 ,  H01L29/165

    CPC classification number: H01L29/7391 ,  H01L29/0843 ,  H01L29/165 ,  H01L29/205

    Abstract: The inventive concepts provide tunneling field effect transistors. The tunneling field effect transistor includes a source region, a drain region, a channel region, and a pocket region. The channel region includes a first material, and is disposed between the source region and the drain region. The pocket region includes a second material, and is disposed between the source region and the drain region. The channel region includes a first region adjacent to the source region, and a second region adjacent to the drain region. A first energy band gap of the first region is smaller than a second energy band gap of the second region, and a third energy band gap of the pocket region is different from the first energy band gap and the second energy band gap.

    Abstract translation: 本发明构思提供了隧穿场效应晶体管。 隧道场效应晶体管包括源极区，漏极区，沟道区和穴区。 沟道区域包括第一材料，并且设置在源极区域和漏极区域之间。 袋区域包括第二材料，并且设置在源极区域和漏极区域之间。 沟道区域包括与源极区域相邻的第一区域和与漏极区域相邻的第二区域。 第一区域的第一能带隙小于第二区域的第二能带隙，并且袋区域的第三能带隙与第一能带隙和第二能带隙不同。

    SEMICONDUCTOR DEVICE
    6.
    发明申请
    SEMICONDUCTOR DEVICE 有权
    半导体器件

    公开(公告)号：US20140367741A1

    公开(公告)日：2014-12-18

    申请号：US14155192

    申请日：2014-01-14

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jung-Gil YANG ,  Sang-Su KIM ,  Chang-Jae YANG

    IPC: H01L29/04 ,  H01L29/78

    CPC classification number: H01L29/04 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0207 ,  H01L27/092 ,  H01L27/0924 ,  H01L27/1104 ,  H01L27/1211 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/66651 ,  H01L29/78 ,  H01L29/7848

    Abstract: Provided is a semiconductor device comprising a substrate including a first area and a second area, first through third crystalline layers sequentially stacked on the first area and having first through third lattice constants, respectively, a first gate electrode formed on the third crystalline layer, fourth and fifth crystalline layers sequentially stacked on the second area and having fourth and fifth lattice constants, respectively, and a second gate electrode formed on the fifth crystalline layer, wherein the third lattice constant is greater than the second lattice constant, the second lattice constant is greater than the first lattice constant, and the fifth lattice constant is smaller than the fourth lattice constant.

    Abstract translation: 本发明提供一种半导体器件，包括：包括第一区域和第二区域的衬底，分别依次层叠在第一区域上并具有第一至第三晶格常数的第一至第三晶体层，形成在第三晶体层上的第一栅电极，第四晶体管 和分别依次层叠在第二区域上并具有第四和第五晶格常数的第五晶体层和形成在第五晶体层上的第二栅电极，其中第三晶格常数大于第二晶格常数，第二晶格常数为 大于第一晶格常数，第五晶格常数小于第四晶格常数。

    SEMICONDUCTOR DEVICES
    7.
    发明申请
    SEMICONDUCTOR DEVICES 有权

    公开(公告)号：US20220238707A1

    公开(公告)日：2022-07-28

    申请号：US17659571

    申请日：2022-04-18

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Jung-Gil YANG ,  Beom-Jin PARK ,  Seung-Min SONG ,  Geum-Jong BAE ,  Dong-Il BAE

    IPC: H01L29/78 ,  H01L29/06 ,  H01L29/66 ,  H01L21/308 ,  H01L21/762 ,  H01L21/8234 ,  H01L29/786 ,  H01L29/423 ,  H01L29/775

    Abstract: A semiconductor device includes channels, a gate structure, and a source/drain layer. The channels are disposed at a plurality of levels, respectively, and spaced apart from each other in a vertical direction on an upper surface of a substrate. The gate structure is disposed on the substrate, at least partially surrounds a surface of each of the channels, and extends in a first direction substantially parallel to the upper surface of the substrate. The source/drain layer is disposed at each of opposite sides of the gate structure in a second direction substantially parallel to the upper surface of the substrate and substantially perpendicular to the first direction and is connected to sidewalls of the channels. A length of the gate structure in the second direction changes along the first direction at a first height from the upper surface of the substrate in the vertical direction.

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