公开(公告)号：US20140209976A1

公开(公告)日：2014-07-31

申请号：US14163972

申请日：2014-01-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Chang-Jae Yang ,  Sang-Su KIM ,  Jung-Dal CHOI ,  Sung-Gi HUR

IPC: H01L29/78 ,  H01L29/10

CPC classification number: H01L29/1054 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66575 ,  H01L29/66651 ,  H01L29/66795 ,  H01L29/785

Abstract: A transistor and a method of manufacturing the same are disclosed. The transistor includes a first epitaxial layer, a channel layer, a gate structure and an impurity region. The first epitaxial layer on a substrate includes a silicon-germanium-tin (SixGe1-x-ySny) single crystal having a lattice constant greater than a lattice constant of a germanium (Ge) single crystal. The channel layer is disposed adjacent to the first epitaxial layer. The channel layer includes the germanium single crystal. The gate structure is disposed on the channel layer. The impurity region is disposed at an upper portion of the channel layer adjacent to the gate structure.

Abstract translation: 公开了晶体管及其制造方法。 晶体管包括第一外延层，沟道层，栅极结构和杂质区。 衬底上的第一外延层包括具有大于锗（Ge）单晶的晶格常数的晶格常数的硅 - 锗 - 锡（SixGe1-x-ySny）单晶。 沟道层设置成与第一外延层相邻。 沟道层包括锗单晶。 栅极结构设置在沟道层上。 杂质区设置在与栅极结构相邻的沟道层的上部。

公开(公告)号：US09391134B2

公开(公告)日：2016-07-12

申请号：US14336084

申请日：2014-07-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chang-Jae Yang ,  Sang-Su Kim ,  Jae-Hwan Lee ,  Jung-Dal Choi

IPC: H01L29/06 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/092 ,  H01L27/12

CPC classification number: H01L29/06 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0924 ,  H01L27/1211

Abstract: A fin field effect transistor includes a first fin structure and a second fin structures both protruding from a substrate, first and second gate electrodes on the first and second fin structures, respectively, and a gate dielectric layer between each of the first and second fin structures and the first and second gate electrodes, respectively. Each of the first and second fin structures includes a buffer pattern on the substrate, a channel pattern on the buffer pattern, and an etch stop pattern provided between the channel pattern and the substrate. The etch stop pattern includes a material having an etch resistivity greater than that of the buffer pattern.

Abstract translation: 翅片场效应晶体管包括分别从第一和第二鳍结构上的衬底，第一和第二栅电极突出的第一鳍结构和第二鳍结构，以及在第一鳍和第二鳍结构中的每一个之间的栅极介电层 以及第一和第二栅电极。 第一和第二鳍结构中的每一个包括衬底上的缓冲图案，缓冲图案上的沟道图案，以及设置在沟道图案和衬底之间的蚀刻停止图案。 蚀刻停止图案包括具有大于缓冲图案的蚀刻电阻率的蚀刻电阻率的材料。

公开(公告)号：US09129815B2

公开(公告)日：2015-09-08

申请号：US14155192

申请日：2014-01-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jung-Gil Yang ,  Sang-Su Kim ,  Chang-Jae Yang

IPC: H01L21/02 ,  H01L29/04 ,  H01L29/78

CPC classification number: H01L29/04 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0207 ,  H01L27/092 ,  H01L27/0924 ,  H01L27/1104 ,  H01L27/1211 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/66651 ,  H01L29/78 ,  H01L29/7848

Abstract: Provided is a semiconductor device comprising a substrate including a first area and a second area, first through third crystalline layers sequentially stacked on the first area and having first through third lattice constants, respectively, a first gate electrode formed on the third crystalline layer, fourth and fifth crystalline layers sequentially stacked on the second area and having fourth and fifth lattice constants, respectively, and a second gate electrode formed on the fifth crystalline layer, wherein the third lattice constant is greater than the second lattice constant, the second lattice constant is greater than the first lattice constant, and the fifth lattice constant is smaller than the fourth lattice constant.

Abstract translation: 本发明提供一种半导体器件，包括：包括第一区域和第二区域的衬底，分别依次层叠在第一区域上并具有第一至第三晶格常数的第一至第三晶体层，形成在第三晶体层上的第一栅电极，第四晶体管 和分别依次层叠在第二区域上并具有第四和第五晶格常数的第五晶体层和形成在第五晶体层上的第二栅电极，其中第三晶格常数大于第二晶格常数，第二晶格常数为 大于第一晶格常数，第五晶格常数小于第四晶格常数。