公开(公告)号：US20180151736A1

公开(公告)日：2018-05-31

申请号：US15877563

申请日：2018-01-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Shigenobu Maeda ,  Tae-Yong KWON ,  Sang-Su KIM ,  Jae-Hoo PARK

IPC: H01L29/78 ,  H01L21/8234 ,  H01L29/66 ,  H01L27/088 ,  H01L29/165 ,  H01L21/02 ,  H01L29/08 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/161 ,  H01L29/16

CPC classification number: H01L29/7848 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823878 ,  H01L27/0886 ,  H01L27/0922 ,  H01L27/0924 ,  H01L29/0847 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/785

Abstract: Methods of forming a semiconductor device may include forming a fin-type active pattern that extends in a first direction on a substrate, the fin-type active pattern including a lower pattern on the substrate and an upper pattern on the lower pattern. A field insulating layer is formed on the substrate, the sidewalls of the fin-type active pattern, and a portion upper pattern protruding further away from the substrate than a top surface of the field insulating layer. A dummy gate pattern that intersects the fin-type active pattern and that extends in a second direction that is different from the first direction is formed. The methods include forming dummy gate spacers on side walls of the dummy gate pattern, forming recesses in the fin-type active pattern on both sides of the dummy gate pattern and forming source and drain regions on both sides of the dummy gate pattern.

公开(公告)号：US20150090958A1

公开(公告)日：2015-04-02

申请号：US14489418

申请日：2014-09-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jung-Gil YANG ,  Sang-Su KIM ,  Sung-Gi HUR

IPC: H01L27/088 ,  H01L29/267 ,  H01L29/78 ,  H01L29/06 ,  H01L29/20

CPC classification number: H01L29/0673 ,  H01L21/02233 ,  H01L21/823412 ,  H01L27/088 ,  H01L27/092 ,  H01L29/0642 ,  H01L29/0676 ,  H01L29/068 ,  H01L29/0847 ,  H01L29/16 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/20 ,  H01L29/267 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66742 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/78684 ,  H01L29/78696

Abstract: A semiconductor device includes at least one nanowire that is disposed over a substrate, extends to be spaced apart from the substrate, and includes a channel region, a gate that surrounds at least a part of the channel region, and a gate dielectric film that is disposed between the channel region and the gate. A source/drain region that contacts one end of the at least one nanowire is formed in a semiconductor layer that extends from the substrate to the one end of the at least one nanowire. Insulating spacers are formed between the substrate and the at least one nanowire. The insulating spacers are disposed between the gate and the source/drain region and are formed of a material that is different from a material of the gate dielectric film.

Abstract translation: 半导体器件包括至少一个纳米线，其被布置在衬底上，延伸成与衬底间隔开，并且包括通道区域，围绕沟道区域的至少一部分的栅极和栅极电介质膜，栅极电介质膜是 设置在通道区域和栅极之间。 接触至少一个纳米线的一端的源/漏区形成在从衬底延伸到至少一个纳米线的一端的半导体层中。 在衬底和至少一个纳米线之间形成绝缘间隔物。 绝缘垫片设置在栅极和源极/漏极区域之间，并且由与栅极电介质膜的材料不同的材料形成。

公开(公告)号：US20140209976A1

公开(公告)日：2014-07-31

申请号：US14163972

申请日：2014-01-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Chang-Jae Yang ,  Sang-Su KIM ,  Jung-Dal CHOI ,  Sung-Gi HUR

IPC: H01L29/78 ,  H01L29/10

CPC classification number: H01L29/1054 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66575 ,  H01L29/66651 ,  H01L29/66795 ,  H01L29/785

Abstract: A transistor and a method of manufacturing the same are disclosed. The transistor includes a first epitaxial layer, a channel layer, a gate structure and an impurity region. The first epitaxial layer on a substrate includes a silicon-germanium-tin (SixGe1-x-ySny) single crystal having a lattice constant greater than a lattice constant of a germanium (Ge) single crystal. The channel layer is disposed adjacent to the first epitaxial layer. The channel layer includes the germanium single crystal. The gate structure is disposed on the channel layer. The impurity region is disposed at an upper portion of the channel layer adjacent to the gate structure.

Abstract translation: 公开了晶体管及其制造方法。 晶体管包括第一外延层，沟道层，栅极结构和杂质区。 衬底上的第一外延层包括具有大于锗（Ge）单晶的晶格常数的晶格常数的硅 - 锗 - 锡（SixGe1-x-ySny）单晶。 沟道层设置成与第一外延层相邻。 沟道层包括锗单晶。 栅极结构设置在沟道层上。 杂质区设置在与栅极结构相邻的沟道层的上部。

公开(公告)号：US20150200289A1

公开(公告)日：2015-07-16

申请号：US14570331

申请日：2014-12-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Xin-Gui ZHANG ,  Tae-Yong KWON ,  Jung-Gil YANG ,  Sang-Su KIM

IPC: H01L29/78 ,  H01L29/205 ,  H01L29/165

CPC classification number: H01L29/7391 ,  H01L29/0843 ,  H01L29/165 ,  H01L29/205

Abstract: The inventive concepts provide tunneling field effect transistors. The tunneling field effect transistor includes a source region, a drain region, a channel region, and a pocket region. The channel region includes a first material, and is disposed between the source region and the drain region. The pocket region includes a second material, and is disposed between the source region and the drain region. The channel region includes a first region adjacent to the source region, and a second region adjacent to the drain region. A first energy band gap of the first region is smaller than a second energy band gap of the second region, and a third energy band gap of the pocket region is different from the first energy band gap and the second energy band gap.

Abstract translation: 本发明构思提供了隧穿场效应晶体管。 隧道场效应晶体管包括源极区，漏极区，沟道区和穴区。 沟道区域包括第一材料，并且设置在源极区域和漏极区域之间。 袋区域包括第二材料，并且设置在源极区域和漏极区域之间。 沟道区域包括与源极区域相邻的第一区域和与漏极区域相邻的第二区域。 第一区域的第一能带隙小于第二区域的第二能带隙，并且袋区域的第三能带隙与第一能带隙和第二能带隙不同。

公开(公告)号：US20200373387A1

公开(公告)日：2020-11-26

申请号：US16993514

申请日：2020-08-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jung-Han LEE ,  Jae-Hwan LEE ,  Sang-Su KIM ,  Hwan-Wook CHOI ,  Tae-Jong LEE ,  Seung-Mo HA

IPC: H01L29/06 ,  H01L27/088 ,  H01L21/8234

Abstract: A semiconductor device includes a plurality of active fins defined by an isolation layer on a substrate, a gate structure on the active fins and the isolation layer, and a gate spacer structure covering a sidewall of the gate structure. A sidewall of the gate structure includes first, second, and third regions having first, second, and third slopes, respectively. The second slope increases from a bottom toward a top of the second region. The second slope has a value at the bottom of the second region less than the first slope. The third slope is greater than the second slope.

公开(公告)号：US20200091286A1

公开(公告)日：2020-03-19

申请号：US16694031

申请日：2019-11-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jung-Han LEE ,  Jae-Hwan LEE ,  Sang-Su KIM ,  Hwan-Wook CHOI ,  Tae-Jong LEE ,  Seung-Mo HA

IPC: H01L29/06 ,  H01L27/088 ,  H01L21/8234

Abstract: A semiconductor device includes a plurality of active fins defined by an isolation layer on a substrate, a gate structure on the active fins and the isolation layer, and a gate spacer structure covering a sidewall of the gate structure. A sidewall of the gate structure includes first, second, and third regions having first, second, and third slopes, respectively. The second slope increases from a bottom toward a top of the second region. The second slope has a value at the bottom of the second region less than the first slope. The third slope is greater than the second slope.

公开(公告)号：US20160204277A1

公开(公告)日：2016-07-14

申请号：US15075888

申请日：2016-03-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jung-Gil YANG ,  Sang-Su KIM ,  Sung-Gi HUR

IPC: H01L29/786 ,  H01L21/02 ,  H01L29/66 ,  H01L29/06 ,  H01L29/423

CPC classification number: H01L29/0673 ,  H01L21/02233 ,  H01L21/823412 ,  H01L27/088 ,  H01L27/092 ,  H01L29/0642 ,  H01L29/0676 ,  H01L29/068 ,  H01L29/0847 ,  H01L29/16 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/20 ,  H01L29/267 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66742 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/78684 ,  H01L29/78696

Abstract: A semiconductor device includes at least one nanowire that is disposed over a substrate, extends to be spaced apart from the substrate, and includes a channel region, a gate that surrounds at least a part of the channel region, and a gate dielectric film that is disposed between the channel region and the gate. A source/drain region that contacts one end of the at least one nanowire is formed in a semiconductor layer that extends from the substrate to the one end of the at least one nanowire. Insulating spacers are formed between the substrate and the at least one nanowire. The insulating spacers are disposed between the gate and the source/drain region and are formed of a material that is different from a material of the gate dielectric film.

公开(公告)号：US20150035009A1

公开(公告)日：2015-02-05

申请号：US14336084

申请日：2014-07-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chang-Jae YANG ,  Sang-Su KIM ,  Jae-Hwan LEE ,  Jung-Dal CHOI

IPC: H01L29/78 ,  H01L29/06

CPC classification number: H01L29/06 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0924 ,  H01L27/1211

Abstract: A fin field effect transistor includes a first fin structure and a second fin structures both protruding from a substrate, first and second gate electrodes on the first and second fin structures, respectively, and a gate dielectric layer between each of the first and second fin structures and the first and second gate electrodes, respectively. Each of the first and second fin structures includes a buffer pattern on the substrate, a channel pattern on the buffer pattern, and an etch stop pattern provided between the channel pattern and the substrate. The etch stop pattern includes a material having an etch resistivity greater than that of the buffer pattern.

Abstract translation: 翅片场效应晶体管包括分别从第一和第二鳍结构上的衬底，第一和第二栅电极突出的第一鳍结构和第二鳍结构，以及在第一鳍和第二鳍结构中的每一个之间的栅极介电层 以及第一和第二栅电极。 第一和第二鳍结构中的每一个包括衬底上的缓冲图案，缓冲图案上的沟道图案，以及设置在沟道图案和衬底之间的蚀刻停止图案。 蚀刻停止图案包括具有大于缓冲图案的蚀刻电阻率的蚀刻电阻率的材料。

公开(公告)号：US20170103916A1

公开(公告)日：2017-04-13

申请号：US15182024

申请日：2016-06-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yong-Ho JEON ,  Sang-Su KIM ,  Cheol KIM ,  Yong-Suk TAK ,  Myung-Geun SONG ,  Gi-Gwan PARK

IPC: H01L21/768 ,  H01L29/08 ,  H01L29/161 ,  H01L29/16 ,  H01L29/49 ,  H01L29/78 ,  H01L23/535 ,  H01L21/8238 ,  H01L29/66 ,  H01L27/092 ,  H01L29/165

CPC classification number: H01L21/76897 ,  H01L21/823425 ,  H01L21/823431 ,  H01L21/823468 ,  H01L21/823475 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823842 ,  H01L21/823864 ,  H01L21/823871 ,  H01L23/535 ,  H01L27/0886 ,  H01L27/0924 ,  H01L29/0847 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/7848

Abstract: A semiconductor device, including a first fin-type pattern; a first gate spacer on the first fin-type pattern, intersecting the first fin-type pattern, and including an upper portion and a lower portion; a second gate spacer on the first fin-type pattern, intersecting the first fin-type pattern, and being spaced apart from the first gate spacer; a first trench defined by the first gate spacer and the second gate spacer; a first gate electrode partially filling the first trench; a first capping pattern on the first gate electrode and filling the first trench; and an interlayer insulating layer covering an upper surface of the capping pattern, a width of the upper portion of the first gate spacer decreasing as a distance from an upper surface of the first fin-type pattern increases, and an outer sidewall of the upper portion of the first gate spacer contacting the interlayer insulating layer.

公开(公告)号：US20170047402A1

公开(公告)日：2017-02-16

申请号：US15339690

申请日：2016-10-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jung-Gil YANG ,  Sang-Su KIM ,  Sung-Gi HUR

IPC: H01L29/06 ,  H01L29/08 ,  H01L29/161 ,  H01L29/66 ,  H01L29/20 ,  H01L27/088 ,  H01L29/786 ,  H01L29/423 ,  H01L29/16

CPC classification number: H01L29/0673 ,  H01L21/02233 ,  H01L21/823412 ,  H01L27/088 ,  H01L27/092 ,  H01L29/0642 ,  H01L29/0676 ,  H01L29/068 ,  H01L29/0847 ,  H01L29/16 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/20 ,  H01L29/267 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66742 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/78684 ,  H01L29/78696

Abstract: A semiconductor device includes at least one nanowire that is disposed over a substrate, extends to be spaced apart from the substrate, and includes a channel region, a gate that surrounds at least a part of the channel region, and a gate dielectric film that is disposed between the channel region and the gate. A source/drain region that contacts one end of the at least one nanowire is formed in a semiconductor layer that extends from the substrate to the one end of the at least one nanowire. Insulating spacers are formed between the substrate and the at least one nanowire. The insulating spacers are disposed between the gate and the source/drain region and are formed of a material that is different from a material of the gate dielectric film.

Abstract translation: 半导体器件包括至少一个纳米线，其被布置在衬底上，延伸成与衬底间隔开，并且包括通道区域，围绕沟道区域的至少一部分的栅极和栅极电介质膜，栅极电介质膜是 设置在通道区域和栅极之间。 接触至少一个纳米线的一端的源/漏区形成在从衬底延伸到至少一个纳米线的一端的半导体层中。 在衬底和至少一个纳米线之间形成绝缘间隔物。 绝缘垫片设置在栅极和源极/漏极区域之间，并且由与栅极电介质膜的材料不同的材料形成。