公开(公告)号：US20210399003A1

公开(公告)日：2021-12-23

申请号：US17149967

申请日：2021-01-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Donghyun SHIN ,  Minkyu KANG ,  Seorim MOON ,  Seunggi MIN ,  Sungmin PARK ,  Jongmin LEE

IPC: H01L27/11573 ,  H01L23/535 ,  H01L27/11582 ,  H01L21/768

Abstract: A three-dimensional semiconductor memory device includes a peripheral circuit structure, a cell array structure above the peripheral circuit structure, and peripheral contact via structures connecting the cell array structure to the peripheral circuit structure, the peripheral contact via structures including a first peripheral contact via structure in a first through region in the peripheral circuit structure, and a second peripheral contact via structure in a second through region in the peripheral circuit structure, the second through region being spaced apart from the first through region above the peripheral circuit structure, and a difference between a second critical dimension of the second peripheral contact via structure and a first critical dimension of the first peripheral contact via structure being differently configured according to material layers included in the second through region and the first through region.

公开(公告)号：US20250142804A1

公开(公告)日：2025-05-01

申请号：US18734052

申请日：2024-06-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Iljae SHIN ,  Kiseok LEE ,  Seokhan PARK ,  Sungmin PARK ,  Dongjun LEE

IPC: H10B12/00

Abstract: A semiconductor device includes gate electrodes extending in a first horizontal direction on a memory cell region and stacked and spaced apart from each other in a vertical direction, back-gate electrodes extending between the gate electrodes in the first horizontal direction and stacked and spaced apart from each other in the vertical direction, vertical conductive patterns extending in the vertical direction and spaced apart from each other in the first horizontal direction on the memory cell region, active layers between the gate electrodes and the back-gate electrodes, extending in a second horizontal direction intersecting with the first horizontal direction, and electrically connected to the vertical conductive patterns on the memory cell region, and a through-plug extending in the vertical direction and in contact with side surfaces of the back-gate electrodes.

公开(公告)号：US20250003139A1

公开(公告)日：2025-01-02

申请号：US18758886

申请日：2024-06-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Juyoung KIM ,  Ohjin KWON ,  Dohaeng KIM ,  Seongryeol MYEONG ,  Sungmin PARK ,  Jewoo BANG ,  Sooyoung LEE

IPC: D06F58/20 ,  D06F34/14 ,  D06F58/02 ,  D06F58/24 ,  D06F103/58 ,  D06F105/02 ,  D06F105/26 ,  D06F105/36

Abstract: A dryer including a main body; a drum inside the main body to receive an object for drying; a heat pump to supply hot and dry air to the drum, and including an evaporator, compressor, and condenser, wherein the evaporator, compressor, and condenser are configured to circulate a refrigerant through the evaporator, the compressor, and the condenser; a condensate tank to store condensate generated by the evaporator; and a connection pipe between the condenser and the evaporator, with at least a portion of the connection pipe being in the condensate tank, wherein the dryer is configured so that refrigerant that has been heat-exchanged with external air in the condenser, and discharged from the condenser, then passes through the connection pipe so as to additionally exchange heat with the condensate in the condensate tank while passing through the at least a portion of the connection pipe in the condensate tank.

公开(公告)号：US20240313853A1

公开(公告)日：2024-09-19

申请号：US18628169

申请日：2024-04-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dongki KWON ,  Yein KIM ,  Hyunil KIM ,  Sungmin PARK ,  Junghun LEE ,  Yonggil HAN

IPC: H04B7/185 ,  H04W4/02

CPC classification number: H04B7/18513 ,  H04W4/026

Abstract: According to embodiments, an electronic device is provided. The electronic device comprises an antenna, memory storing instructions, a display, and at least one processor. The instructions cause, when executed by the at least one processor, the electronic device to execute an application related to a satellite, display, within a display area of the application, an antenna indicator indicating a reference range of a direction of the antenna of the electronic device, obtain azimuth angle information and elevation angle information for a relative direction of the satellite in respect to the direction of the antenna of the electronic device, display, on a horizontal position corresponding to the azimuth angle information within the display area and a vertical position corresponding to the elevation angle information within the display area, a satellite indicator indicating the relative direction of the satellite, the satellite indicator is moved with respect to the antenna indicator in accordance with change of an orientation of the electronic device.

公开(公告)号：US20150007157A1

公开(公告)日：2015-01-01

申请号：US14319935

申请日：2014-06-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sungmin PARK ,  Sangho KIM ,  Boseok MOON ,  Jae-Hyun PARK

IPC: G06F9/445

CPC classification number: G06F8/65 ,  H04M1/72525

Abstract: A method and an apparatus for updating an application are provided. An electronic device activates an automatic update of an installed application, designates the application as one group of one or more groups distinguished according to an update period. The electronic device controls to update the application after a time point of an update period corresponding to the designated group.

Abstract translation: 提供了一种更新应用程序的方法和装置。 电子设备激活已安装应用的自动更新，将应用指定为根据更新周期区分的一个或多个组的一组。 电子设备控制在对应于指定组的更新周期的时间点之后更新应用。

公开(公告)号：US20250089239A1

公开(公告)日：2025-03-13

申请号：US18804207

申请日：2024-08-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sungmin PARK ,  Jinwoo HAN ,  Seokhan PARK ,  Gyuhwan OH ,  Bowon YOO

IPC: H10B12/00

Abstract: Provided is a semiconductor memory device including a plurality of word lines extending in a first horizontal direction, a plurality of channel patterns adjacent to a plurality of word line structures, arranged in a row in the first horizontal direction, and extending in a vertical direction, a plurality of bit lines extending in a second horizontal direction different from the first horizontal direction and electrically connected to a plurality of channel patterns, the plurality of word lines adjacent to the plurality of channel patterns, and the plurality of channel patterns on the bit lines, a shield conductive layer arranged below the plurality of bit lines and extending in the vertical direction between the bit lines, and a cover insulating layer arranged between the plurality of bit lines and the shield conductive layer. In a plan view the shield conductive layer comprises a main body unit and a pad unit, the plurality of bit lines overlapping the main body unit in the vertical direction, and a pad unit extending from the main body unit but the plurality of bit lines not overlapping the pad unit in the vertical direction.