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    SEMICONDUCTOR MEMORY DEVICE
    1.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE 有权

    公开(公告)号：US20240422961A1

    公开(公告)日：2024-12-19

    申请号：US18640513

    申请日：2024-04-19

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Joongchan SHIN ,  Seokhan PARK ,  Kiseok LEE ,  Moonyoung JEONG ,  Jinwoo HAN

    IPC: H10B12/00

    Abstract: A semiconductor memory device includes a plurality of word lines extending in a first horizontal direction, a plurality of back gate lines extending in the first horizontal direction and alternately arranged with the plurality of word lines in a second horizontal direction different from the first horizontal direction, a plurality of channel layers extending in a vertical direction between a word line and a back gate line adjacent to each other among the plurality of word lines and the plurality of back gate lines, to correspond to columns in the first horizontal direction, a plurality of bit lines extending in the second horizontal direction on the plurality of word lines, the plurality of back gate lines, and the plurality of channel layers and electrically connected to the plurality of channel layers, and a plurality of memory structures electrically connected to the plurality of channel layers.

    SEMICONDUCTOR DEVICE
    2.
    发明申请
    SEMICONDUCTOR DEVICE 有权

    公开(公告)号：US20240421223A1

    公开(公告)日：2024-12-19

    申请号：US18631839

    申请日：2024-04-10

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Joongchan SHIN ,  Seokhan PARK ,  Kiseok LEE ,  Moonyoung JEONG ,  Jinwoo HAN

    IPC: H01L29/78 ,  H10B12/00

    Abstract: A semiconductor device includes a substrate, a bit line extending in a first direction on the substrate, a first active pattern and a second active pattern on the bit line, a back gate electrode extending in a second direction perpendicular to the first direction across the bit line, and a word line extending in the second direction, wherein the first active pattern and the second active pattern have a minor symmetrical shape with respect to the back gate electrode when viewed in a third direction perpendicular to the first direction and the second direction.

    SEMICONDUCTOR DEVICES
    4.
    发明申请
    SEMICONDUCTOR DEVICES 有权

    公开(公告)号：US20220199793A1

    公开(公告)日：2022-06-23

    申请号：US17443553

    申请日：2021-07-27

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Hyuncheol KIM ,  Yongseok KIM ,  Ilgweon KIM ,  Seokhan PARK ,  Kyunghwan LEE ,  Jaeho HONG

    IPC: H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L23/482

    Abstract: A semiconductor device includes a plurality of semiconductor structures disposed on a substrate, a first conductive pattern, a first conductive pattern, a gate insulation pattern, a second conductive pattern and a second impurity region. Each of the semiconductor structures includes a first semiconductor pattern that has a linear shape that extends in a first direction and second semiconductor patterns that protrude from an upper surface of the first semiconductor pattern in a vertical direction. The semiconductor structures are spaced apart from each other in a second direction perpendicular to the first direction. The first conductive pattern is formed between the first semiconductor patterns. The first impurity region is formed in an opening in the first semiconductor pattern adjacent to a first sidewall of the second semiconductor pattern. The first impurity region includes an impurity diffusion harrier pattern and a polysilicon pattern doped with impurities

    SEMICONDUCTOR MEMORY DEVICE
    5.
    发明公开
    SEMICONDUCTOR MEMORY DEVICE 审中-公开

    公开(公告)号：US20240147706A1

    公开(公告)日：2024-05-02

    申请号：US18370149

    申请日：2023-09-19

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Keunui KIM ,  Kiseok LEE ,  Eunsuk JANG ,  Seokhan PARK ,  Seok-Ho SHIN ,  Joongchan SHIN ,  Moonyoung JEONG

    IPC: H10B12/00

    CPC classification number: H10B12/488 ,  H10B12/315 ,  H10B12/482 ,  H10B12/50

    Abstract: A semiconductor memory device may include a substrate, a bit line extending in a first direction on the substrate, a first word line and a second word line extending in a second direction to cross the bit line, a back-gate electrode extending in the second direction between the first word line and the second word line, first and second active patterns disposed between the first and second word lines and the back-gate electrode and connected to the bit line, contact patterns coupled to the first and second active patterns, respectively, a first back-gate capping pattern between the contact patterns and the back-gate electrode, and first gate capping patterns between the contact patterns and the first and second word lines. The first back-gate capping pattern and the first gate capping pattern may have first and second seams, which are extended in the second direction and are located at different vertical levels.

    SEMICONDUCTOR MEMORY DEVICE
    6.
    发明公开
    SEMICONDUCTOR MEMORY DEVICE 审中-公开

    公开(公告)号：US20240147701A1

    公开(公告)日：2024-05-02

    申请号：US18238790

    申请日：2023-08-28

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Kiseok LEE ,  Eunju CHO ,  Keunnam KIM ,  Seokhan PARK ,  Seok-Ho SHIN ,  Joongchan SHIN ,  Heechan YOON

    IPC: H10B12/00

    CPC classification number: H10B12/482 ,  H10B12/315 ,  H10B12/485 ,  H10B12/488 ,  H10B12/50

    Abstract: A semiconductor memory device may include a substrate including a cell array region and a connection region, bit lines provided on the substrate and extending in a first direction, first and second active patterns alternately arranged in the first direction on each of the bit lines, back-gate electrodes disposed between adjacent ones of the first and second active patterns and extended in a second direction to cross the bit lines, first and second word lines disposed adjacent to the first and second active patterns respectively and extending in the second direction, and a shielding conductive pattern including line portions, which are respectively disposed between adjacent ones of the bit lines, and a plate portion, which is connected in common to the line portions. A length of the line portions of the shielding conductive pattern in the first direction may be shorter than that of the bit lines.

    SEMICONDUCTOR MEMORY DEVICE
    7.
    发明公开
    SEMICONDUCTOR MEMORY DEVICE 审中-公开

    公开(公告)号：US20230363143A1

    公开(公告)日：2023-11-09

    申请号：US18182539

    申请日：2023-03-13

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Kiseok LEE ,  Moonyoung JEONG ,  Keunnam KIM ,  Seokhan PARK

    IPC: H10B12/00 ,  H10B80/00

    CPC classification number: H10B12/315 ,  H10B12/482 ,  H10B12/05 ,  H10B80/00

    Abstract: A semiconductor memory device is disclosed. The semiconductor memory device may include a bit line extending in a first direction, first and second active patterns disposed on the bit line, a back-gate electrode, which is disposed between the first and second active patterns and is extended in a second direction to cross the bit line, a first word line, which is provided at a side of the first active pattern and is extended in the second direction, a second word line, which is provided at an opposite side of the second active pattern and is extended in the second direction, and contact patterns coupled to the first and second active patterns, respectively.

    SEMICONDUCTOR MEMORY DEVICE
    9.
    发明公开
    SEMICONDUCTOR MEMORY DEVICE 审中-公开

    公开(公告)号：US20240147707A1

    公开(公告)日：2024-05-02

    申请号：US18242817

    申请日：2023-09-06

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Taegyu KANG ,  Taehyuk KIM ,  Seok-Ho SHIN ,  Keunnam KIM ,  Seokhan PARK ,  Joongchan SHIN ,  Kiseok LEE

    IPC: H10B12/00 ,  H01L23/522

    CPC classification number: H10B12/50 ,  H01L23/5225 ,  H10B12/09 ,  H10B12/315 ,  H10B12/482

    Abstract: A semiconductor memory device may include a substrate including a cell array region and a peripheral circuit region, an active pattern on the cell array region of the substrate, a peripheral active pattern on the peripheral circuit region of the substrate, a peripheral gate electrode disposed on a top surface of the peripheral active pattern, a first interlayer insulating pattern provided on the cell array region to cover a top surface of the active pattern, a first etch stop layer covering the first interlayer insulating pattern and the peripheral gate electrode with a uniform thickness, and a second interlayer insulating pattern disposed on the first etch stop layer and in the peripheral circuit region. In the cell array region, the second interlayer insulating pattern may have a top surface, which is located at substantially the same level as a top surface of the first etch stop layer.

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