公开(公告)号：US20250081444A1

公开(公告)日：2025-03-06

申请号：US18610790

申请日：2024-03-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Bowon YOO ,  Seokhan PARK ,  Gyuhwan OH ,  Jinwoo HAN

IPC: H10B12/00

Abstract: A semiconductor memory device includes a peripheral gate structure, bit lines above the peripheral gate structure, being apart from each other in a first direction, and extending in a second direction different from the first direction, first and second active patterns above the bit lines and apart from each other in the second direction, first and second word lines between the first and active patterns and being adjacent to the first and second active patterns, respectively, a first back gate electrode corresponding to the first word line, the first active pattern being between the first back gate electrode and the first word line, a second back gate electrode corresponding to the second word line, the second active being between the second back gate electrode and the second word line, and a word line shielding structure between the first word line and the second word line.

公开(公告)号：US20250107071A1

公开(公告)日：2025-03-27

申请号：US18671624

申请日：2024-05-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Taegyu KANG ,  Keunui KIM ,  Seokhan PARK ,  Joongchan SHIN ,  Gyuhwan OH ,  Bowon YOO ,  Kiseok LEE ,  Sangho LEE ,  Eunsuk JANG ,  Moonyoung JEONG

IPC: H10B12/00

Abstract: A semiconductor device comprising: a substrate; bit lines on the substrate; word lines on the bit lines, wherein the word lines are spaced apart from each other in a first direction; activation patterns between the word lines; a back gate electrode between the activation patterns, wherein the back gate electrode extends in a second direction; and a first gate separation pattern between the word lines in the first direction, wherein a portion of the word lines is a space between the activation patterns in the second direction and the word lines extend around the activation patterns, wherein the word lines and the first gate separation pattern each include a first surface facing the bit lines and a second surface opposite to the first surface in a third direction, wherein the first gate separation pattern is closer than the word lines to the bit lines in the third direction.

公开(公告)号：US20250107075A1

公开(公告)日：2025-03-27

申请号：US18809859

申请日：2024-08-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyunghwan KIM ,  Joongchan SHIN ,  Hyungeun CHOI ,  Taegyu KANG ,  Keunui KIM ,  Bowon YOO

IPC: H10B12/00

Abstract: A semiconductor device includes a substrate including a cell array area and an interface area, bit lines on the cell array area and extending in a first horizontal direction, back gate lines on the bit lines and extending in a second direction, insulating blocks on the interface area and each overlapping the back gate lines in the second direction, word lines among which each pair of two adjacent word lines are on both sides of a corresponding back gate line, respectively, and extending on a sidewall of a corresponding insulating block, active semiconductor layers each between a corresponding back gate line and a corresponding word line on the cell array area and having one end electrically connected to a corresponding bit line, and a word line contact on the interface area and on a corresponding word line and a corresponding insulating block adjacent thereto.

公开(公告)号：US20250098154A1

公开(公告)日：2025-03-20

申请号：US18825176

申请日：2024-09-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sanghyun SUNG ,  Seokhan PARK ,  Gyuhwan OH ,  Bowon YOO ,  Jinwoo HAN

IPC: H10B12/00

Abstract: A semiconductor device includes bit lines, which are apart from each other in a first direction and extend in a second direction that crosses the first direction, above a top surface of a substrate, comb-type insulating patterns arranged among the bit lines in the first direction and apart from each other in the second direction, line insulating layers apart from each other in the first direction, extending in the second direction, and covering the bit lines and portions of the comb-type insulating patterns from below, and a conductive line shield layer covering the line insulating layers and the other portions of the comb-type insulating patterns from below.

公开(公告)号：US20250089239A1

公开(公告)日：2025-03-13

申请号：US18804207

申请日：2024-08-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sungmin PARK ,  Jinwoo HAN ,  Seokhan PARK ,  Gyuhwan OH ,  Bowon YOO

IPC: H10B12/00

Abstract: Provided is a semiconductor memory device including a plurality of word lines extending in a first horizontal direction, a plurality of channel patterns adjacent to a plurality of word line structures, arranged in a row in the first horizontal direction, and extending in a vertical direction, a plurality of bit lines extending in a second horizontal direction different from the first horizontal direction and electrically connected to a plurality of channel patterns, the plurality of word lines adjacent to the plurality of channel patterns, and the plurality of channel patterns on the bit lines, a shield conductive layer arranged below the plurality of bit lines and extending in the vertical direction between the bit lines, and a cover insulating layer arranged between the plurality of bit lines and the shield conductive layer. In a plan view the shield conductive layer comprises a main body unit and a pad unit, the plurality of bit lines overlapping the main body unit in the vertical direction, and a pad unit extending from the main body unit but the plurality of bit lines not overlapping the pad unit in the vertical direction.

公开(公告)号：US20250081441A1

公开(公告)日：2025-03-06

申请号：US18414959

申请日：2024-01-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Bowon YOO ,  Seokhan PARK ,  Gyuhwan OH ,  Jinwoo HAN

IPC: H10B12/00

Abstract: A semiconductor memory device includes a bit line on a peripheral gate structure and extending in a second direction different from a first direction; a shielding structure adjacent to the bit line on the peripheral gate structure and extending in the second direction; a back gate electrode on the bit line and the shielding structure and extending in the first direction; a first word line extending in the first direction and on one side of the back gate electrode in the second direction, and a second word line placed on another side of the back gate electrode, the first and second word lines on the bit line and the shielding structure; and a first activation pattern between the back gate electrode and the first word line and a second activation pattern, the first and second activation patterns on the bit line, wherein the shielding structure includes a low-dielectric material.