公开(公告)号：US09076886B2

公开(公告)日：2015-07-07

申请号：US13960323

申请日：2013-08-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dong-Il Park ,  Ae-Gyeong Kim ,  Jong-Sam Kim ,  Kyoung-Eun Uhm ,  Tae-Cheol Lee ,  Yong-Sang Jeong ,  Jin-Ha Jeong

IPC: H01L29/66 ,  H01L21/8234 ,  H01L29/423 ,  H01L29/40 ,  H01L29/78

CPC classification number: H01L21/823468 ,  H01L21/823456 ,  H01L21/823462 ,  H01L29/401 ,  H01L29/4236 ,  H01L29/7834

Abstract: A semiconductor device and a method for fabricating the same are provided. The semiconductor device includes a device isolation region, a trench formed in the device isolation region, a void connected to the trench in the device isolation region, a first mask pattern formed along sidewalls of the trench and protruding inwardly with respect to the void, a gate insulating film formed along the sidewall of the void, and a gate electrode filling the trench and at least a portion of the void.

Abstract translation: 提供了一种半导体器件及其制造方法。 半导体器件包括器件隔离区域，形成在器件隔离区域中的沟槽，连接到器件隔离区域中的沟槽的空穴，沿着沟槽的侧壁形成并相对于空隙向内突出的第一掩模图案， 沿着空隙的侧壁形成的栅极绝缘膜，以及填充沟槽和至少一部分空隙的栅电极。

公开(公告)号：US20140042528A1

公开(公告)日：2014-02-13

申请号：US13960323

申请日：2013-08-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dong-Il Park ,  Ae-Gyeong Kim ,  Jong-Sam Kim ,  Kyoung-Eun Uhm ,  Tae-Cheol Lee ,  Yong-Sang Jeong ,  Jin-Ha Jeong

IPC: H01L21/8234 ,  H01L29/40 ,  H01L29/423

CPC classification number: H01L21/823468 ,  H01L21/823456 ,  H01L21/823462 ,  H01L29/401 ,  H01L29/4236 ,  H01L29/7834

Abstract: A semiconductor device and a method for fabricating the same are provided. The semiconductor device includes a device isolation region, a trench formed in the device isolation region, a void connected to the trench in the device isolation region, a first mask pattern formed along sidewalls of the trench and protruding inwardly with respect to the void, a gate insulating film formed along the sidewall of the void, and a gate electrode filling the trench and at least a portion of the void.

Abstract translation: 提供了一种半导体器件及其制造方法。 半导体器件包括器件隔离区域，形成在器件隔离区域中的沟槽，连接到器件隔离区域中的沟槽的空穴，沿着沟槽的侧壁形成并相对于空隙向内突出的第一掩模图案， 沿着空隙的侧壁形成的栅极绝缘膜，以及填充沟槽和至少一部分空隙的栅电极。