公开(公告)号：US09076886B2

公开(公告)日：2015-07-07

申请号：US13960323

申请日：2013-08-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dong-Il Park ,  Ae-Gyeong Kim ,  Jong-Sam Kim ,  Kyoung-Eun Uhm ,  Tae-Cheol Lee ,  Yong-Sang Jeong ,  Jin-Ha Jeong

IPC: H01L29/66 ,  H01L21/8234 ,  H01L29/423 ,  H01L29/40 ,  H01L29/78

CPC classification number: H01L21/823468 ,  H01L21/823456 ,  H01L21/823462 ,  H01L29/401 ,  H01L29/4236 ,  H01L29/7834

Abstract: A semiconductor device and a method for fabricating the same are provided. The semiconductor device includes a device isolation region, a trench formed in the device isolation region, a void connected to the trench in the device isolation region, a first mask pattern formed along sidewalls of the trench and protruding inwardly with respect to the void, a gate insulating film formed along the sidewall of the void, and a gate electrode filling the trench and at least a portion of the void.

Abstract translation: 提供了一种半导体器件及其制造方法。 半导体器件包括器件隔离区域，形成在器件隔离区域中的沟槽，连接到器件隔离区域中的沟槽的空穴，沿着沟槽的侧壁形成并相对于空隙向内突出的第一掩模图案， 沿着空隙的侧壁形成的栅极绝缘膜，以及填充沟槽和至少一部分空隙的栅电极。

公开(公告)号：US20140042528A1

公开(公告)日：2014-02-13

申请号：US13960323

申请日：2013-08-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dong-Il Park ,  Ae-Gyeong Kim ,  Jong-Sam Kim ,  Kyoung-Eun Uhm ,  Tae-Cheol Lee ,  Yong-Sang Jeong ,  Jin-Ha Jeong

IPC: H01L21/8234 ,  H01L29/40 ,  H01L29/423

CPC classification number: H01L21/823468 ,  H01L21/823456 ,  H01L21/823462 ,  H01L29/401 ,  H01L29/4236 ,  H01L29/7834

Abstract: A semiconductor device and a method for fabricating the same are provided. The semiconductor device includes a device isolation region, a trench formed in the device isolation region, a void connected to the trench in the device isolation region, a first mask pattern formed along sidewalls of the trench and protruding inwardly with respect to the void, a gate insulating film formed along the sidewall of the void, and a gate electrode filling the trench and at least a portion of the void.

Abstract translation: 提供了一种半导体器件及其制造方法。 半导体器件包括器件隔离区域，形成在器件隔离区域中的沟槽，连接到器件隔离区域中的沟槽的空穴，沿着沟槽的侧壁形成并相对于空隙向内突出的第一掩模图案， 沿着空隙的侧壁形成的栅极绝缘膜，以及填充沟槽和至少一部分空隙的栅电极。

公开(公告)号：US09859158B2

公开(公告)日：2018-01-02

申请号：US15239364

申请日：2016-08-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyunglyong Kang ,  Youngmok Kim ,  Hodae Oh ,  Kyoung-Eun Uhm

IPC: H01L21/311 ,  H01L21/768 ,  H01L21/28 ,  H01L29/423 ,  H01L21/8234 ,  H01L29/49 ,  H01L29/51 ,  H01L29/78

CPC classification number: H01L21/76877 ,  H01L21/28123 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/823462 ,  H01L21/823481 ,  H01L29/42368 ,  H01L29/4933 ,  H01L29/513 ,  H01L29/517 ,  H01L29/7833

Abstract: A method for manufacturing a semiconductor device includes forming a device isolation layer in a substrate to define an active region, forming a gate insulating layer covering at least a portion of the active region, forming a gate electrode on the gate insulating layer, and forming an interlayer insulating layer on the gate electrode. The gate insulating layer includes a first portion overlapping with the active region and a second portion overlapping with the device isolation layer. The forming of the gate insulating layer includes etching at least a part of the second portion of the gate insulating layer to thin the part of the second portion of the gate insulating layer.

公开(公告)号：US08987797B2

公开(公告)日：2015-03-24

申请号：US14050744

申请日：2013-10-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Oh-Kyum Kwon ,  Tae-Jung Lee ,  Kyoung-Eun Uhm ,  Byung-Sun Kim

IPC: H01L27/108 ,  H01L27/11 ,  H01L29/78 ,  H01L27/115 ,  H01L29/94

CPC classification number: H01L29/78 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11529 ,  H01L27/11558 ,  H01L29/94

Abstract: A nonvolatile memory device has a first active region and a second active region defined in a substrate by a device isolation layer, a Metal Oxide Silicon Field-Effect Transistor (MOSFET) disposed on the first active region and including a first electrode pattern, and a Metal Oxide Silicon (MOS) capacitor disposed on the second active region and including a second electrode pattern, and in which the first electrode pattern is narrower in the widthwise direction of the channel of the MOSFET than the first active region.

Abstract translation: 非易失性存储器件具有通过器件隔离层在衬底中限定的第一有源区和第二有源区，设置在第一有源区上并包括第一电极图的金属氧化物半导体场效应晶体管（MOSFET） 金属氧化物硅（MOS）电容器，其设置在第二有源区并且包括第二电极图案，并且其中第一电极图案在MOSFET的沟道的宽度方向上比第一有源区域窄。