公开(公告)号：US20140317471A1

公开(公告)日：2014-10-23

申请号：US14225725

申请日：2014-03-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jang-woo RYU ,  Chul-sung PARK ,  Tae-young OH ,  Chan-yong LEE ,  Tae-Seong JANG ,  Hoi-ju CHUNG ,  Gong-heum HAN

IPC: G06F11/10 ,  H03M13/13

CPC classification number: G06F11/10 ,  G06F11/1048 ,  H03M13/13

Abstract: A semiconductor memory device may comprise: at least one bank, each of the at least one bank including a plurality of memory cells; an error-correcting code (ECC) calculator configured to generate syndrome data for detecting an error bit from among parallel data bits read out from the plurality of memory cells of each of the at least one bank; an ECC corrector separated from the ECC calculator, the ECC corrector configured to correct the error bit from among the parallel data bits by using the syndrome data and configured to output error-corrected parallel data bits; and/or a data serializer configured to receive the error-corrected parallel data bits and configured to convert the error-corrected parallel data bits into serial data bits.

Abstract translation: 半导体存储器件可以包括：至少一个存储体，所述至少一个存储体中的每一个包括多个存储器单元; 纠错码（ECC）计算器，被配置为从从所述至少一个存储体中的每一个的所述多个存储器单元读出的并行数据位中生成用于检测错误位的校正子数据; 与ECC计算器分离的ECC校正器，ECC校正器被配置为通过使用校正子数据来校正并行数据位中的误差位，并且被配置为输出纠错的并行数据位; 和/或数据串行器，被配置为接收经纠错的并行数据位，并且被配置为将经纠错的并行数据位转换为串行数据位。

公开(公告)号：US20140331006A1

公开(公告)日：2014-11-06

申请号：US14208339

申请日：2014-03-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hoi-Ju CHUNG ,  Chul-Sung PARK ,  Tae-Seong JANG ,  Gong-Heum HAN ,  Jang-Woo RYU

IPC: G11C7/10

CPC classification number: G11C7/1096 ,  G11C7/1006 ,  G11C7/1009

Abstract: A semiconductor memory device includes a memory cell array, a data inversion/mask interface and a write circuit. The data inversion/mask interface receives a data block including a plurality of unit data, each of the plurality of unit data having a first data size, and the data inversion/mask interface selectively enables each data mask signal associated with each of the plurality of unit data based on a number of first data bits in a second data size of each unit data. The second data size is smaller than a first data size of the unit data. The write circuit receives the data block and performs a masked write operation that selectively writes each of the plurality of unit data in the memory cell array in response to the data mask signal.

Abstract translation: 半导体存储器件包括存储单元阵列，数据反转/掩模接口和写入电路。 数据反转/掩模接口接收包括多个单元数据的数据块，多个单元数据中的每一个具有第一数据大小，并且数据反转/掩码接口选择性地启用与多个单元数据中的每一个相关联的每个数据掩码信号 基于每个单位数据的第二数据大小中的第一数据位的数量的单元数据。 第二数据大小小于单位数据的第一数据大小。 写入电路接收数据块并执行屏蔽写入操作，其响应于数据屏蔽信号选择性地将多个单元数据中的每一个写入存储单元阵列。