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    SEMICONDUCTOR MEMORY DEVICES AND MEMORY SYSTEMS INCLUDING THE SAME
    3.
    发明申请
    SEMICONDUCTOR MEMORY DEVICES AND MEMORY SYSTEMS INCLUDING THE SAME 审中-公开

    公开(公告)号：US20170109231A1

    公开(公告)日：2017-04-20

    申请号：US15204536

    申请日：2016-07-07

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Sang-Uhn CHA ,  Hoi-Ju CHUNG

    IPC: G06F11/10 ,  G11C29/52 ,  G06F3/06

    CPC classification number: G06F11/1068 ,  G06F11/1048 ,  G11C29/52 ,  G11C2029/0411

    Abstract: A semiconductor memory device includes a memory cell array, an error correction circuit and a control logic circuit. The error correction circuit performs an error correction code (ECC) encoding on write data to be stored in the memory cell array, and performs an ECC decoding on read data from the memory cell array. The control logic circuit controls access to the memory cell array and generates an engine configuration selection signal based on a command. The error correction circuit reconfigures a number of units for which ECC including the ECC encoding and the ECC decoding is performed, in response to the engine configuration selection signal.

    SEMICONDUCTOR MEMORY DEVICES AND MEMORY SYSTEMS INCLUDING THE SAME
    4.
    发明申请
    SEMICONDUCTOR MEMORY DEVICES AND MEMORY SYSTEMS INCLUDING THE SAME 有权
    半导体存储器件和存储器系统，包括它们

    公开(公告)号：US20170031756A1

    公开(公告)日：2017-02-02

    申请号：US15209043

    申请日：2016-07-13

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Hoi-Ju CHUNG ,  Sang-Uhn CHA

    IPC: G06F11/10 ,  G11C29/52 ,  G06F3/06 ,  G11C11/4072

    CPC classification number: G06F11/1068 ,  G06F3/0619 ,  G06F3/064 ,  G06F3/0679 ,  G06F11/1048 ,  G11C7/20 ,  G11C11/1675 ,  G11C11/4072 ,  G11C2029/0407

    Abstract: A semiconductor memory device is provided. The semiconductor memory device includes a memory cell array, an input/output (I/O) gating circuit and an error correction circuit. The memory cell array includes a plurality of memory cells. The I/O gating circuit, before performing a normal memory operation on the memory cell array by a first unit, performs a cell data initializing operation by writing initializing bits in the memory cell array by a second unit different from the first unit. The error correction circuit performs an error correction code (ECC) encoding and an ECC decoding on a target page of the memory cell array by the second unit, based on the initializing bits. Therefore, power consumption in performing write operation may be reduced.

    Abstract translation: 提供半导体存储器件。 半导体存储器件包括存储单元阵列，输入/输出（I / O）门控电路和纠错电路。 存储单元阵列包括多个存储单元。 I / O选通电路在通过第一单元对存储单元阵列执行正常存储器操作之前，通过用与第一单元不同的第二单元将存储单元阵列中的位初始化写入来执行单元数据初始化操作。 误差校正电路基于初始化比特，在第二单元的存储单元阵列的目标页面上执行纠错码（ECC）编码和ECC解码。 因此，可以减少执行写入操作时的功耗。

    NONVOLATILE MEMORY DEVICE HAVING MULTIPLE READ CIRCUITS AND USING VARIABLE RESISTIVE MATERIALS
    6.
    发明申请
    NONVOLATILE MEMORY DEVICE HAVING MULTIPLE READ CIRCUITS AND USING VARIABLE RESISTIVE MATERIALS 有权
    具有多个读取电路和使用可变电阻材料的非易失性存储器件

    公开(公告)号：US20140247646A1

    公开(公告)日：2014-09-04

    申请号：US14171873

    申请日：2014-02-04

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Hyo-Jin KWON ,  Hoi-Ju CHUNG ,  Chae-Hoon KIM ,  Yong-Jin KWON ,  Eun-Hye PARK ,  Yong-Jun LEE

    IPC: G11C13/00

    CPC classification number: G11C13/004 ,  G11C13/0002 ,  G11C13/0004 ,  G11C13/0061 ,  G11C2213/72

    Abstract: A nonvolatile memory device includes a memory array having multiple nonvolatile memory cells, a first read circuit and a second read circuit. The first read circuit is configured to read first data from the memory array during a first read operation and to provide one or more protection signals indicating a victim period during the first read operation. The second read circuit is configured to read second data from the memory array during a second read operation and to provide one or more check signals indicating an aggressor period during the second read operation.

    Abstract translation: 非易失性存储器件包括具有多个非易失性存储单元的存储器阵列，第一读取电路和第二读取电路。 第一读取电路被配置为在第一读取操作期间从存储器阵列读取第一数据，并且在第一读取操作期间提供指示受害时段的一个或多个保护信号。 第二读取电路被配置为在第二读取操作期间从存储器阵列读取第二数据，并且在第二读取操作期间提供指示侵略者周期的一个或多个检查信号。

    SEMICONDUCTOR MEMORY DEVICES
    10.
    发明申请
    SEMICONDUCTOR MEMORY DEVICES 审中-公开
    半导体存储器件

    公开(公告)号：US20140331006A1

    公开(公告)日：2014-11-06

    申请号：US14208339

    申请日：2014-03-13

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Hoi-Ju CHUNG ,  Chul-Sung PARK ,  Tae-Seong JANG ,  Gong-Heum HAN ,  Jang-Woo RYU

    IPC: G11C7/10

    CPC classification number: G11C7/1096 ,  G11C7/1006 ,  G11C7/1009

    Abstract: A semiconductor memory device includes a memory cell array, a data inversion/mask interface and a write circuit. The data inversion/mask interface receives a data block including a plurality of unit data, each of the plurality of unit data having a first data size, and the data inversion/mask interface selectively enables each data mask signal associated with each of the plurality of unit data based on a number of first data bits in a second data size of each unit data. The second data size is smaller than a first data size of the unit data. The write circuit receives the data block and performs a masked write operation that selectively writes each of the plurality of unit data in the memory cell array in response to the data mask signal.

    Abstract translation: 半导体存储器件包括存储单元阵列，数据反转/掩模接口和写入电路。 数据反转/掩模接口接收包括多个单元数据的数据块，多个单元数据中的每一个具有第一数据大小，并且数据反转/掩码接口选择性地启用与多个单元数据中的每一个相关联的每个数据掩码信号 基于每个单位数据的第二数据大小中的第一数据位的数量的单元数据。 第二数据大小小于单位数据的第一数据大小。 写入电路接收数据块并执行屏蔽写入操作，其响应于数据屏蔽信号选择性地将多个单元数据中的每一个写入存储单元阵列。

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