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公开(公告)号:US12185534B2
公开(公告)日:2024-12-31
申请号:US17649562
申请日:2022-02-01
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Junhyoung Kim , Byunggon Park , Seungmin Lee , Kangmin Kim , Taemin Eom , Byungkwan You
IPC: H10B41/40 , H01L23/522 , H01L23/528 , H01L23/532 , H01L23/538 , H01L23/60 , H01L27/02 , H10B41/10 , H10B41/27 , H10B41/35 , H10B41/50 , H10B43/10 , H10B43/27 , H10B43/35 , H10B43/40 , H10B43/50
Abstract: An integrated circuit device includes a substrate, a peripheral wiring circuit that includes a bypass via and is disposed on the substrate, a peripheral circuit that includes an interlayer insulating layer surrounding at least a portion of the peripheral wiring circuit, and a memory cell array disposed on and overlapping the peripheral circuit. The memory cell array includes a base substrate, a plurality of gate lines disposed on the base substrate, and a plurality of channels penetrating the plurality of gate lines. The integrated circuit device further includes a barrier layer interposed between the peripheral circuit and the memory cell array. The barrier layer includes a bypass hole penetrating from a top surface to a lower surface of the barrier layer. The bypass via is disposed in the bypass hole.
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公开(公告)号:US20220384467A1
公开(公告)日:2022-12-01
申请号:US17649562
申请日:2022-02-01
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Junhyoung Kim , Byunggon Park , Seungmin Lee , Kangmin Kim , Taemin Eom , Byungkwan You
IPC: H01L27/11526 , H01L27/11519 , H01L23/522 , H01L23/528 , H01L27/11524 , H01L27/11556 , H01L27/11565 , H01L27/1157 , H01L27/11573 , H01L27/11582
Abstract: An integrated circuit device includes a substrate, a peripheral wiring circuit that includes a bypass via and is disposed on the substrate, a peripheral circuit that includes an interlayer insulating layer surrounding at least a portion of the peripheral wiring circuit, and a memory cell array disposed on and overlapping the peripheral circuit. The memory cell array includes a base substrate, a plurality of gate lines disposed on the base substrate, and a plurality of channels penetrating the plurality of gate lines. The integrated circuit device further includes a barrier layer interposed between the peripheral circuit and the memory cell array. The barrier layer includes a bypass hole penetrating from a top surface to a lower surface of the barrier layer. The bypass via is disposed in the bypass hole.
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公开(公告)号:US20220375862A1
公开(公告)日:2022-11-24
申请号:US17563275
申请日:2021-12-28
Applicant: Samsung Electronics Co., Ltd.
Inventor: Junhyoung Kim , Kangmin Kim , Taemin Eom , Seungmin Lee , Changsun Hwang
IPC: H01L23/535 , H01L27/11556 , H01L27/11582
Abstract: A semiconductor device includes a substrate including a cell array region and a contact region; a plurality of gate electrodes arranged on the substrate in a first direction perpendicular to an upper surface of the substrate, the plurality of gate electrodes being extending in the cell array region and the contact region; a plurality of channel structures penetrating the plurality of gate electrodes in the first direction in the cell array region; a plurality of dummy channel structures penetrating the plurality of gate electrodes in the first direction in the contact region; a plurality of cell gate contacts extending in the first direction and each electrically connected to a respective one of the plurality of gate electrodes in the contact region; and a plurality of dummy contacts extending in the first direction on the plurality of dummy channel structures.
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公开(公告)号:US20220367359A1
公开(公告)日:2022-11-17
申请号:US17567249
申请日:2022-01-03
Applicant: Samsung Electronics Co., Ltd.
Inventor: Junhyoung Kim , Kangmin Kim , Changhwan Lee , Taemin Eom , Seungmin Lee
IPC: H01L23/535 , H01L27/11556 , H01L27/11529 , H01L27/11582 , H01L27/11573
Abstract: A semiconductor device includes a first structure including a substrate, circuit devices, a lower interconnection structure electrically connected to the circuit devices, and a second structure on the first structure. The second structure includes a conductive plate layer; gate electrodes on the conductive plate layer and extending in a first direction; separation regions penetrating through the gate electrodes and extending in the first direction; channel structures penetrating through the gate electrodes and respectively including a channel layer; through-contact plugs spaced apart from the gate electrodes and extending in the vertical direction to be electrically connected to the lower interconnection structure of the first structure; first and second contacts electrically connected to the channel layer and the through-contact plugs, respectively; bitlines electrically connecting at least one of each of the first and second contacts to each other; and dummy contacts connected to the bitlines and spaced apart from the through-contact plugs.
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