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公开(公告)号:US20230077532A1
公开(公告)日:2023-03-16
申请号:US17946761
申请日:2022-09-16
发明人: Wookyu KIM , Changbeom Kim , Taejun Yoo , Seungmin Lee
IPC分类号: G06F30/392 , G06F30/394 , G06F30/327
摘要: A standard cell and an integrated circuit including the same are is provided. The standard cell is provided in first and second rows. The standard cell includes: a first circuit region provided in the first row and including a plurality of first transistors; a second circuit region provided in the second row and including a plurality of second transistors; a first input pin provided in the first circuit region and configured to receive a first input signal; and a second input pin provided in the second circuit region and configured to receive a second input signal. The first input signal is input to gate terminals of each of the plurality of first transistors, and the second input signal is input to gate terminals of each of the plurality of second transistors. The first circuit region is symmetric with respect to a second horizontal direction and the second circuit region is symmetric with respect to the second horizontal direction.
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公开(公告)号:US20230005949A1
公开(公告)日:2023-01-05
申请号:US17720453
申请日:2022-04-14
发明人: Seungmin Lee , Kangmin Kim , Junhyoung Kim , Yonghoon Son , Joonsung Lim
IPC分类号: H01L27/11575 , H01L23/535 , H01L49/02 , H01L27/11582 , H01L27/11573
摘要: A semiconductor device includes a first structure including a peripheral circuit and a second structure on the first structure. The second structure includes: a stack structure including first and second stack structures; separation structures passing through the first stack structure; a memory vertical structure between the separation structures and passing through the first stack structure; and a capacitor including first and second capacitor electrodes passing through the second stack structure and extending parallel to each other. The first stack structure includes spaced apart gate electrodes and interlayer insulating layers alternately stacked therewith. The second stack structure includes spaced apart first insulating layers, and second insulating layers alternately stacked therewith. Each of the first and second capacitor electrodes has a linear shape. The first and second insulating layers include a different material from each other. The second insulating layers include the same material as the interlayer insulating layers.
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3.
公开(公告)号:US11329187B2
公开(公告)日:2022-05-10
申请号:US16883363
申请日:2020-05-26
发明人: Kyungwook Hwang , Jungel Ryu , Sungjin Kang , Jongmyeong Kim , Jehong Oh , Euijoon Yoon , Seungmin Lee , Junsik Hwang
摘要: A method of aligning micro LEDs and a method of manufacturing a micro LED display using the same are provided. The method of aligning micro LEDs includes providing micro LEDs, each having a first surface that has a first maximum width and a second surface opposite to the first surface and has a second maximum width that is greater than the first maximum width, providing a transfer substrate including a transfer mold that has an array of openings, each of the openings being configured to accommodate the first surface of a corresponding micro LED and not accommodate the second surface of the corresponding micro LED and aligning the micro LEDs in one direction in the openings of the transfer mold by inserting the micro LEDs into the openings of the transfer mold so that the first surface of each of the micro LEDs is positioned within a corresponding opening.
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公开(公告)号:USD796355S1
公开(公告)日:2017-09-05
申请号:US29555238
申请日:2016-02-19
设计人: Chul-Ho Cho , Myeong Su Cheon , Sangkyu Kim , Seungmin Lee
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公开(公告)号:US12034997B2
公开(公告)日:2024-07-09
申请号:US17680568
申请日:2022-02-25
发明人: Jaeki Kyoun , Heejin Ko , Hyunjee Kwak , Sunyoung Kim , Seungmin Lee , Yoojin Choi , Jeonghye Choi
IPC分类号: H04N21/431 , H04N21/422 , H04N21/443 , H04N21/81
CPC分类号: H04N21/4312 , H04N21/42202 , H04N21/4438 , H04N21/8173
摘要: A display device includes a display configured to output a broadcast content or a content for an interior decoration function, a memory storing a first layout for surrounding the broadcast content and a second layout for surrounding the content for the interior decoration function, and a processor operatively connected to the display and the memory, wherein the processor removes the first layout, enlarges the broadcast content, and outputs the enlarged broadcast content through the display based on a first user input, and enlarges portions of the content for the interior decoration function and of the second layout and outputs the enlarged portions of the content for the interior decoration function and of the second layout through the display based on a second user input.
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6.
公开(公告)号:US11887936B2
公开(公告)日:2024-01-30
申请号:US17469952
申请日:2021-09-09
发明人: Kwanyong Kim , Sungwon Shin , Seungmin Lee , Juyoung Lim , Wonseok Cho
IPC分类号: H01L23/544 , H01L23/532 , H01L23/528 , H10B41/46
CPC分类号: H01L23/544 , H01L23/5283 , H01L23/53295 , H10B41/46
摘要: A semiconductor device includes a first stack structure on a substrate, and a second stack structure on the first stack structure. A channel structure extends through the first stack structure and the second stack structure. A first auxiliary stack structure including a plurality of first insulating layers and a plurality of first mold layers are alternately stacked on the substrate. An alignment key extends into the first auxiliary stack structure and protrudes to a higher level than an uppermost end of the first stack structure. A second auxiliary stack structure is disposed on the first auxiliary stack structure and the alignment key, and includes a plurality of second insulating layers and a plurality of second mold layers alternately stacked. The second auxiliary stack structure includes a protrusion aligned with the alignment key.
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公开(公告)号:US11437396B2
公开(公告)日:2022-09-06
申请号:US17032128
申请日:2020-09-25
发明人: Junhyoung Kim , Jisung Cheon , Yoonhwan Son , Seungmin Lee
IPC分类号: H01L27/11578 , H01L27/11568 , H01L27/11573
摘要: A semiconductor device includes a lower structure; a first upper structure including lower gate layers on the lower structure; a second upper structure including upper gate layers on the first upper structure; separation structures penetrating the first and second upper structures on the lower structure; a memory vertical structure penetrating the lower and upper gate layers between the separation structures; and a first contact plug penetrating the first and second upper structures and spaced apart from the lower and upper gate layers. Each of the first contact plug and the memory vertical structure includes a lateral surface having a bent portion. The bent portion of the lateral surface is disposed between a first height level on which an uppermost gate layer of the lower gate layers is disposed and a second height level on which a lowermost gate layer of the upper gate layers is disposed.
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8.
公开(公告)号:US20200348599A1
公开(公告)日:2020-11-05
申请号:US16676588
申请日:2019-11-07
发明人: Keunhee Bai , Jinhong Park , Jinseok Heo , Seungmin Lee , Suntaek Lim
IPC分类号: G03F7/20 , H01L21/268
摘要: Disclosed are a system for fabricating a semiconductor device and a method of fabricating a semiconductor device. The system may include a chamber, an extreme ultraviolet (EUV) source in the chamber and configured to generate an EUV beam, an optical system on the EUV source and configured to provide the EUV beam to a substrate, a substrate stage in the chamber and configured to receive the substrate, a reticle stage in the chamber and configured to hold a reticle that is configured to project the EUV beam onto the substrate, and a particle collector between the reticle and the optical system and configured to allow for a selective transmission of the EUV beam and to remove a particle.
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公开(公告)号:US12133384B2
公开(公告)日:2024-10-29
申请号:US18352182
申请日:2023-07-13
发明人: Junhyoung Kim , Jisung Cheon , Yoonhwan Son , Seungmin Lee
摘要: A semiconductor device includes a lower structure; a first upper structure including lower gate layers on the lower structure; a second upper structure including upper gate layers on the first upper structure; separation structures penetrating the first and second upper structures on the lower structure; a memory vertical structure penetrating the lower and upper gate layers between the separation structures; and a first contact plug penetrating the first and second upper structures and spaced apart from the lower and upper gate layers. Each of the first contact plug and the memory vertical structure includes a lateral surface having a bent portion. The bent portion of the lateral surface is disposed between a first height level on which an uppermost gate layer of the lower gate layers is disposed and a second height level on which a lowermost gate layer of the upper gate layers is disposed.
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公开(公告)号:US20240312938A1
公开(公告)日:2024-09-19
申请号:US18674610
申请日:2024-05-24
发明人: Junhyoung Kim , Taemok Gwon , Seungmin Lee
IPC分类号: H01L23/00 , H01L23/522 , H01L25/00 , H01L25/065 , H01L25/18 , H10B41/27 , H10B43/27
CPC分类号: H01L24/08 , H01L23/5226 , H01L24/80 , H01L25/0657 , H01L25/18 , H01L25/50 , H10B41/27 , H10B43/27 , H01L2224/08145 , H01L2224/80895 , H01L2224/80896 , H01L2924/1431 , H01L2924/14511
摘要: A semiconductor device includes first gate electrodes, a first channel structure penetrating the first gate electrodes and including a first channel layer and a first channel filling insulating layer, second gate electrodes above the first gate electrodes, a second channel structure penetrating the second gate electrodes and including a second channel layer and a second channel filling insulating layer, and a central wiring layer between the first gate electrodes and the second gate electrodes and connected to the first channel layer and the second channel layer, wherein the first channel layer and the second channel layer are connected to each other in a region surrounded by the central wiring layer, and the first channel filling insulating layer and the second channel filling insulating layer are connected to each other in a region surrounded by the central wiring layer.
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