公开(公告)号：US20220028877A1

公开(公告)日：2022-01-27

申请号：US17204380

申请日：2021-03-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Changsun Hwang ,  Gihwan Kim ,  Hansol Seok ,  Jongheun Lim ,  Kiseok Jang

IPC: H01L27/11573 ,  H01L23/535 ,  H01L27/11556 ,  H01L27/11529 ,  H01L27/11582

Abstract: An integrated circuit device includes a vertical stack of nonvolatile memory cells on a substrate, which are configured as a vertical NAND string of memory cells. This vertical stack of nonvolatile memory cells includes a plurality of gate patterns, which are spaced apart from each other by corresponding electrically insulating layers. A dummy mold structure is also provided on the substrate. The dummy mold structure includes a vertical stack of sacrificial layers, which are spaced apart from each other by corresponding electrically insulating layers. An insulation pattern is provided, which fills a dish-shaped recess in a first one of the sacrificial layers in the vertical stack of sacrificial layers. This insulation pattern has an upper surface that is coplanar with an upper surface of the first one of the sacrificial layers.

公开(公告)号：US11963361B2

公开(公告)日：2024-04-16

申请号：US17140277

申请日：2021-01-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Changsun Hwang ,  Youngjin Kwon ,  Gihwan Kim ,  Hansol Seok ,  Dongseog Eun ,  Jongheun Lim

IPC: H10B41/40 ,  H01L23/522 ,  H10B41/27 ,  H10B41/41 ,  H10B43/27 ,  H10B43/40

CPC classification number: H10B43/40 ,  H01L23/5226 ,  H10B41/27 ,  H10B41/41 ,  H10B43/27

Abstract: An integrated circuit device includes: a substrate having a cell region, a peripheral circuit region, and an interconnection region between the cell region and the peripheral circuit region; a first cell stack structure and a second cell stack structure on the first cell stack structure, each including a plurality of insulating layers and a plurality of word line structures alternately stacked on the substrate; and a dummy stack structure located at a same vertical level as the second cell stack structure, and including a plurality of dummy insulating layers and a plurality of dummy support layers alternately stacked in the peripheral circuit region.

公开(公告)号：US20240224533A1

公开(公告)日：2024-07-04

申请号：US18605115

申请日：2024-03-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Changsun Hwang ,  Youngjin Kwon ,  Gihwan Kim ,  Hansol Seok ,  Dongseog Eun ,  Jongheun Lim

IPC: H10B43/40 ,  H01L23/522 ,  H10B41/27 ,  H10B41/41 ,  H10B43/27

CPC classification number: H10B43/40 ,  H01L23/5226 ,  H10B41/27 ,  H10B41/41 ,  H10B43/27

Abstract: An integrated circuit device includes: a substrate having a cell region, a peripheral circuit region, and an interconnection region between the cell region and the peripheral circuit region; a first cell stack structure and a second cell stack structure on the first cell stack structure, each including a plurality of insulating layers and a plurality of word line structures alternately stacked on the substrate; and a dummy stack structure located at a same vertical level as the second cell stack structure, and including a plurality of dummy insulating layers and a plurality of dummy support layers alternately stacked in the peripheral circuit region.

公开(公告)号：US20220375862A1

公开(公告)日：2022-11-24

申请号：US17563275

申请日：2021-12-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junhyoung Kim ,  Kangmin Kim ,  Taemin Eom ,  Seungmin Lee ,  Changsun Hwang

IPC: H01L23/535 ,  H01L27/11556 ,  H01L27/11582

Abstract: A semiconductor device includes a substrate including a cell array region and a contact region; a plurality of gate electrodes arranged on the substrate in a first direction perpendicular to an upper surface of the substrate, the plurality of gate electrodes being extending in the cell array region and the contact region; a plurality of channel structures penetrating the plurality of gate electrodes in the first direction in the cell array region; a plurality of dummy channel structures penetrating the plurality of gate electrodes in the first direction in the contact region; a plurality of cell gate contacts extending in the first direction and each electrically connected to a respective one of the plurality of gate electrodes in the contact region; and a plurality of dummy contacts extending in the first direction on the plurality of dummy channel structures.

公开(公告)号：US11482448B2

公开(公告)日：2022-10-25

申请号：US17035827

申请日：2020-09-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hansol Seok ,  Chungki Min ,  Changsun Hwang ,  Gihwan Kim ,  Jongheun Lim

IPC: H01L21/768 ,  H01L27/11582 ,  H01L23/522 ,  H01L23/528 ,  H01L23/535

Abstract: Semiconductor devices and methods of forming the same are provided. The methods may include forming a stacked structure that may include a stacking area and a stepped area and may include first layers and second layers alternately stacked. The second layers may have a stepped shape in the stepped area, and the stepped area may include at least one flat area and at least one inclined stepped area. The methods may also include forming a capping insulating layer covering the stacked structure. The capping insulating layer may include a first capping region having a first upper surface and a second capping region having a second upper surface at a lower level than the first upper surface. The methods may further include patterning the capping insulating layer to form protrusions at least one of which overlaps the stepped area and then planarizing the capping insulating layer.