公开(公告)号：US10028375B2

公开(公告)日：2018-07-17

申请号：US15177805

申请日：2016-06-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yong Il Kwon ,  Tah Joon Park ,  Joon Seok Chae ,  Jong Woo Choi

IPC: H05K1/18 ,  H05K1/02 ,  H05K1/14 ,  H05K1/11 ,  H05K1/09 ,  G06K9/00

Abstract: A fingerprint sensing device includes a board having a sensor array, a sub-board disposed on a bottom surface of the board, a circuit element disposed on the bottom surface of the board, and a through hole disposed through the sub-board, wherein the circuit element is further disposed in the through hole. A thickness of the sub-board is substantially similar to a thickness of the circuit element.

公开(公告)号：US09891761B2

公开(公告)日：2018-02-13

申请号：US14206293

申请日：2014-03-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Byeoung Hak Jo ,  Moon Suk Jeong ,  Yong Il Kwon ,  Tah Joon Park

IPC: G06F3/044 ,  G06F3/041

CPC classification number: G06F3/044 ,  G06F3/0416 ,  G06F2203/04111

Abstract: There are provided a touch sensing device and a touchscreen device. The touch sensing device includes: a driving circuit applying a driving signal having a predetermined first period to a node capacitor; a buffer circuit converting capacitance of the node capacitor into a voltage signal; a buffer capacitor being charged and discharged depending on an output voltage from the buffer circuit; and an integration circuit integrating voltages charged in the buffer capacitor, wherein, in a normal touch mode, the buffer circuit integrates capacitance of the node capacitor to generate the voltage signal, and, in a proximity touch mode, the buffer circuit generates the voltage signal by following the voltages charged in the node capacitor.

公开(公告)号：US09851833B2

公开(公告)日：2017-12-26

申请号：US14481018

申请日：2014-09-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yong Il Kwon ,  Byeong Hak Jo ,  Moon Suk Jeong ,  Tah Joon Park

IPC: G06F3/041 ,  G06F1/32 ,  G06G7/186 ,  G06F3/044

CPC classification number: G06F3/0416 ,  G06F1/3262 ,  G06F3/044 ,  G06G7/186 ,  Y02D50/20

Abstract: An integration circuit may include a plurality of switches, at least one operational amplifier, and at least one feedback capacitor, sequentially transfers electrical charges charged in a node capacitor to the feedback capacitor, and integrates the electrical charges. The operational amplifier may be synchronized with a clock signal applied to at least one of the plurality of switches to thereby be operated in one of a normal mode and a low power mode.