LAYOUT DESIGN TOOL
    1.
    发明公开
    LAYOUT DESIGN TOOL 审中-公开

    公开(公告)号:US20230297746A1

    公开(公告)日:2023-09-21

    申请号:US18184902

    申请日:2023-03-16

    CPC classification number: G06F30/31 G06F30/392

    Abstract: A layout design tool for generating a layout graphic based on a first input and a modification input includes a processing circuitry that generates a temporary layout in which a pattern is scripted based on the first input, and modifies the temporary layout based on the modification input to generate the layout graphic, and the processing circuitry designates a plurality of modification regions to be modified on the temporary layout based on the modification input and designates a plurality of transform regions on a background layer, the plurality of modification regions of the temporary layout, and the layout design tool generates a pattern layer by extracting the pattern group included in any one of the plurality of modification regions and generates the layout graphic by placing the pattern layer on the plurality of transform regions of the background layer.

    SEMICONDUCTOR DEVICE
    2.
    发明申请

    公开(公告)号:US20220359424A1

    公开(公告)日:2022-11-10

    申请号:US17734234

    申请日:2022-05-02

    Abstract: A semiconductor memory device may include a substrate, a plurality of lower electrodes on the substrate, and a support structure. The plurality of lower electrodes may extend in a first direction perpendicular to a top surface of the substrate. The support structure may have a flat panel shape. The support structure may contact a side surface of the plurality of lower electrodes and may support the plurality of lower electrodes. The support structure may include a plurality of openings. The support structure may include a first part and a second part. The first part may include the plurality of openings repeated by a first pitch. The second part may include the plurality of openings repeated by a second pitch that is different from the first pitch.

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