公开(公告)号：US20230066341A1

公开(公告)日：2023-03-02

申请号：US17704185

申请日：2022-03-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junmo PARK ,  Yeonho PARK ,  Wangseop LIM ,  Kyubong CHOI

IPC: H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/51

Abstract: A semiconductor device includes a substrate including first and second active regions, first and second active patterns on the first and second active regions, and a gate electrode crossing the first and second active patterns. The gate electrode may include first and second electrode portions on the first and second active regions. The first electrode portion may include a first metal pattern and a second metal pattern on the first metal pattern. The second electrode portion may include a third metal pattern and a fourth metal pattern on the third metal pattern. The first metal pattern may include a first line portion and a first vertical portion extended from the first line portion, and the third metal pattern may include a second line portion and a second vertical portion extended from the second line portion. The first and second vertical portions may be in contact with each other.

公开(公告)号：US20240321980A1

公开(公告)日：2024-09-26

申请号：US18596772

申请日：2024-03-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Doohyun LEE ,  Heonjong SHIN ,  Jaehyun KANG ,  Seonbae KIM ,  Wangseop LIM ,  Seunghyun HWANG

IPC: H01L29/417 ,  H01L29/06 ,  H01L29/08 ,  H01L29/40 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775

CPC classification number: H01L29/41733 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/401 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775

Abstract: An integrated circuit device includes a substrate having a main surface and fin-type active regions protruding in a vertical direction from the main surface and extending lengthwise in a first horizontal direction, gate lines extending parallel to one another in a second horizontal direction perpendicular to the first horizontal direction and crossing the fin-type active regions, source/drain regions on the fin-type active regions between the gate lines, an inter-gate insulation layer covering the source/drain regions between the gate lines, active contacts on and in contact with the source/drain regions, and a buried insulation block between adjacent ones of the source/drain regions in the second horizontal direction, the buried insulation block penetrating through at least a portion of the inter-gate insulation layer and having a top surface in contact with a first active contact of the active contacts.