公开(公告)号：US10804194B2

公开(公告)日：2020-10-13

申请号：US15902806

申请日：2018-02-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Gang Zhang ,  Kwang Soo Kim ,  Won Bong Jung

IPC: H01L23/522 ,  H01L21/68 ,  H01L27/11524 ,  H01L27/11536 ,  H01L27/11556 ,  H01L23/532 ,  H01L21/768 ,  H01L27/11573 ,  H01L27/11565 ,  H01L27/11582 ,  H01L27/11575

Abstract: A semiconductor device comprises a peripheral circuit region provided on a first substrate and including circuit devices and a contact plug extending on the first substrate in a vertical direction; a memory cell region provided on a second substrate disposed above the first substrate and including memory cells; and a through insulating region penetrating through the second substrate on the contact plug and covering an upper surface of the contact plug.

公开(公告)号：US20190051599A1

公开(公告)日：2019-02-14

申请号：US15902806

申请日：2018-02-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Gang Zhang ,  Kwang Soo Kim ,  Won Bong Jung

IPC: H01L23/522 ,  H01L21/768 ,  H01L27/11524 ,  H01L27/11536 ,  H01L27/11556 ,  H01L23/532

Abstract: A semiconductor device comprises a peripheral circuit region provided on a first substrate and including circuit devices and a contact plug extending on the first substrate in a vertical direction; a memory cell region provided on a second substrate disposed above the first substrate and including memory cells; and a through insulating region penetrating through the second substrate on the contact plug and covering an upper surface of the contact plug.

公开(公告)号：US09893077B2

公开(公告)日：2018-02-13

申请号：US15049160

申请日：2016-02-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Phil Ouk Nam ,  Yong Hoon Son ,  Kyung Hyun Kim ,  Byeong Ju Kim ,  Kwang Chul Park ,  Yeon Sil Sohn ,  Jin I Lee ,  Jong Heun Lim ,  Won Bong Jung

IPC: H01L21/00 ,  H01L21/84 ,  H01L21/20 ,  H01L21/36 ,  H01L29/10 ,  H01L29/76 ,  H01L31/036 ,  H01L31/112 ,  H01L27/1157 ,  H01L21/02 ,  H01L27/11573 ,  H01L27/11582

CPC classification number: H01L27/1157 ,  H01L21/02667 ,  H01L21/02675 ,  H01L27/11573 ,  H01L27/11582

Abstract: A memory device, including a first memory region including a first substrate, a plurality of first semiconductor devices on the first substrate, and a first interlayer insulating layer covering the plurality of first semiconductor devices; and a second memory region including a second substrate on the first interlayer insulating layer and a plurality of second semiconductor devices on the second substrate, the second substrate including a first region in a plurality of grooves in the first interlayer insulating layer and a second region including grains extending from the first region, the second region being on an upper surface of the first interlayer insulating layer.