公开(公告)号：US10243584B2

公开(公告)日：2019-03-26

申请号：US15488789

申请日：2017-04-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hye-Seung Yu ,  Sukyong Kang ,  Wonjoo Yun ,  Hyunui Lee ,  Jae-Hun Jung

IPC: H03M13/00 ,  H03M13/09 ,  G06F11/10 ,  G11C29/52

Abstract: A memory device including a parity check circuit and a mask circuit may be provided. The parity check circuit may perform parity check on data sampled according to a data strobe signal, which does not include a post-amble. The mask circuit may generate a parity error signal based on results of the parity check, and output the parity error signal during a time period determined according to a burst length of the data.

公开(公告)号：US10938416B2

公开(公告)日：2021-03-02

申请号：US16262127

申请日：2019-01-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hye-Seung Yu ,  Sukyong Kang ,  Wonjoo Yun ,  Hyunui Lee ,  Jae-Hun Jung

IPC: H03M13/00 ,  H03M13/09 ,  G11C29/52 ,  G06F11/10

Abstract: A memory device including a parity check circuit and a mask circuit may be provided. The parity check circuit may perform parity check on data sampled according to a data strobe signal, which does not include a post-amble. The mask circuit may generate a parity error signal based on results of the parity check, and output the parity error signal during a time period determined according to a burst length of the data.