公开(公告)号：US10509070B2

公开(公告)日：2019-12-17

申请号：US16106127

申请日：2018-08-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Won-Joo Yun ,  Sukyong Kang ,  Hye-Seung Yu ,  Hyunui Lee

IPC: G01R31/28 ,  G01R31/02 ,  G01R31/26 ,  H01L21/66 ,  H01L25/065 ,  H03K17/687 ,  G11C29/00 ,  G11C29/02 ,  G11C29/50 ,  G11C5/02

Abstract: Disclosed are a method and a device for detecting a short circuit between adjacent micro-bumps. The method includes setting outputs of a pull-up driver and a pull-down driver of a data output circuit connected with a micro-bump to be suitable for a test type and determining whether a short circuit is generated.

公开(公告)号：US10938416B2

公开(公告)日：2021-03-02

申请号：US16262127

申请日：2019-01-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hye-Seung Yu ,  Sukyong Kang ,  Wonjoo Yun ,  Hyunui Lee ,  Jae-Hun Jung

IPC: H03M13/00 ,  H03M13/09 ,  G11C29/52 ,  G06F11/10

Abstract: A memory device including a parity check circuit and a mask circuit may be provided. The parity check circuit may perform parity check on data sampled according to a data strobe signal, which does not include a post-amble. The mask circuit may generate a parity error signal based on results of the parity check, and output the parity error signal during a time period determined according to a burst length of the data.

公开(公告)号：US20190271742A1

公开(公告)日：2019-09-05

申请号：US16169107

申请日：2018-10-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyunui Lee ,  Hye-Seung Yu ,  Won-Joo Yun

IPC: G01R31/317 ,  G01R31/3177 ,  G11C29/02

Abstract: A semiconductor memory device includes first bumps positioned along a first direction; second bumps positioned in parallel to the first bumps along the first direction; first registers connected with the first bumps; and second registers connected with the second bumps. The first registers and the second registers are sequentially connected and form a shift register.

公开(公告)号：US20180356458A1

公开(公告)日：2018-12-13

申请号：US16106127

申请日：2018-08-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Won-Joo YUN ,  Sukyong Kang ,  Hye-Seung Yu ,  Hyunui Lee

IPC: G01R31/28 ,  H03K17/687 ,  H01L21/66 ,  G01R31/26 ,  G11C29/00 ,  G11C29/02 ,  G11C29/50 ,  G01R31/02 ,  H01L25/065 ,  G11C5/02

Abstract: Disclosed are a method and a device for detecting a short circuit between adjacent micro-bumps. The method includes setting outputs of a pull-up driver and a pull-down driver of a data output circuit connected with a micro-bump to be suitable for a test type and determining whether a short circuit is generated.

公开(公告)号：US09966126B2

公开(公告)日：2018-05-08

申请号：US15486689

申请日：2017-04-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sung-Oh Ahn ,  Sukyong Kang ,  Hye-Seung Yu ,  Jae-Hun Jung

IPC: G11C11/00 ,  G11C11/16 ,  G11C11/4076 ,  G11C13/00 ,  G06F11/10

CPC classification number: G11C11/1693 ,  G06F11/1004 ,  G11C7/1087 ,  G11C7/1093 ,  G11C7/222 ,  G11C11/161 ,  G11C11/4076 ,  G11C11/4093 ,  G11C13/0007 ,  G11C13/004 ,  G11C13/0061 ,  G11C13/0069

Abstract: A delay circuit of a semiconductor memory device includes a delay chain, a first phase converter and a second phase converter. The delay chain is connected between an input terminal and an output terminal, includes 2N delay cells, and delays a first intermediate signal to generate a second intermediate signal. The first phase converter is connected to the input terminal, and provides the first intermediate signal to the delay chain, wherein the first intermediate signal is generated by inverting a phase of an input signal or by maintaining the phase of the input signal in response to a control signal. The second phase converter is connected to the output terminal, and generates an output signal by inverting a phase of the second intermediate signal or by maintaining the phase of the second intermediate signal in response to the control signal.

公开(公告)号：US09959935B2

公开(公告)日：2018-05-01

申请号：US15480724

申请日：2017-04-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sukyong Kang ,  Won-Joo Yun ,  Hye-Seung Yu ,  Hyun-Ui Lee ,  Jae-Hun Jung

IPC: G11C29/12 ,  G11C11/4076 ,  G11C11/4096

CPC classification number: G11C29/12 ,  G11C7/1087 ,  G11C11/4076 ,  G11C11/4093 ,  G11C11/4096 ,  G11C29/022 ,  G11C29/023 ,  G11C29/028 ,  G11C29/1201 ,  G11C29/12015 ,  G11C29/46 ,  G11C2029/1208

Abstract: An input-output circuit includes a reception circuit and a register circuit. The reception circuit operates in accordance with a normal write protocol commonly in a normal write mode and a test write mode. The reception circuit receives a plurality of input signals to generate a plurality of latch signals. The register circuit generates a plurality of test result signals based on the latch signals in the test write mode. The input-output circuit may perform the multiple-input shift register (MISR) function in accordance with the normal write path and the normal write protocol. The MISR function may be performed efficiently without consideration of additional timing adjustment for the test write operation because the MISR function is performed under the same timing condition as the normal write operation.

公开(公告)号：US10908212B2

公开(公告)日：2021-02-02

申请号：US16169107

申请日：2018-10-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyunui Lee ,  Hye-Seung Yu ,  Won-Joo Yun

IPC: G01R31/00 ,  G01R31/317 ,  G11C29/02 ,  G01R31/3177

Abstract: A semiconductor memory device includes first bumps positioned along a first direction; second bumps positioned in parallel to the first bumps along the first direction; first registers connected with the first bumps; and second registers connected with the second bumps. The first registers and the second registers are sequentially connected and form a shift register.

公开(公告)号：US10243584B2

公开(公告)日：2019-03-26

申请号：US15488789

申请日：2017-04-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hye-Seung Yu ,  Sukyong Kang ,  Wonjoo Yun ,  Hyunui Lee ,  Jae-Hun Jung

IPC: H03M13/00 ,  H03M13/09 ,  G06F11/10 ,  G11C29/52

Abstract: A memory device including a parity check circuit and a mask circuit may be provided. The parity check circuit may perform parity check on data sampled according to a data strobe signal, which does not include a post-amble. The mask circuit may generate a parity error signal based on results of the parity check, and output the parity error signal during a time period determined according to a burst length of the data.

公开(公告)号：US10078110B2

公开(公告)日：2018-09-18

申请号：US15295244

申请日：2016-10-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Won-Joo Yun ,  Sukyong Kang ,  Hye-Seung Yu ,  Hyunui Lee

IPC: G01R31/02 ,  G01R31/26 ,  G01R31/28 ,  H01L21/66 ,  H01L25/065 ,  H03K17/687 ,  G11C29/00 ,  G11C29/02 ,  G11C29/50 ,  G11C5/02

CPC classification number: G01R31/2853 ,  G01R31/025 ,  G01R31/26 ,  G01R31/2884 ,  G11C5/025 ,  G11C29/006 ,  G11C29/025 ,  G11C29/50008 ,  H01L22/14 ,  H01L22/34 ,  H01L25/0657 ,  H01L2224/16227 ,  H01L2225/06513 ,  H01L2225/06596 ,  H01L2924/15311 ,  H03K17/6872

Abstract: Disclosed are a method and a device for detecting a short circuit between adjacent micro-bumps. The method includes setting outputs of a pull-up driver and a pull-down driver of a data output circuit connected with a micro-bump to be suitable for a test type and determining whether a short circuit is generated.

公开(公告)号：US20170372764A1

公开(公告)日：2017-12-28

申请号：US15486689

申请日：2017-04-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SUNG-OH AHN ,  Sukyong Kang ,  Hye-Seung Yu ,  Jae-Hun Jung

IPC: G11C11/16 ,  G06F11/10 ,  G11C11/4076 ,  G11C13/00

CPC classification number: G11C11/1693 ,  G06F11/1004 ,  G11C7/1087 ,  G11C7/1093 ,  G11C7/222 ,  G11C11/161 ,  G11C11/4076 ,  G11C11/4093 ,  G11C13/0007 ,  G11C13/004 ,  G11C13/0061 ,  G11C13/0069

Abstract: A delay circuit of a semiconductor memory device includes a delay chain, a first phase converter and a second phase converter. The delay chain is connected between an input terminal and an output terminal, includes 2N delay cells, and delays a first intermediate signal to generate a second intermediate signal. The first phase converter is connected to the input terminal, and provides the first intermediate signal to the delay chain, wherein the first intermediate signal is generated by inverting a phase of an input signal or by maintaining the phase of the input signal in response to a control signal. The second phase converter is connected to the output terminal, and generates an output signal by inverting a phase of the second intermediate signal or by maintaining the phase of the second intermediate signal in response to the control signal.