公开(公告)号：US10243584B2

公开(公告)日：2019-03-26

申请号：US15488789

申请日：2017-04-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hye-Seung Yu ,  Sukyong Kang ,  Wonjoo Yun ,  Hyunui Lee ,  Jae-Hun Jung

IPC: H03M13/00 ,  H03M13/09 ,  G06F11/10 ,  G11C29/52

Abstract: A memory device including a parity check circuit and a mask circuit may be provided. The parity check circuit may perform parity check on data sampled according to a data strobe signal, which does not include a post-amble. The mask circuit may generate a parity error signal based on results of the parity check, and output the parity error signal during a time period determined according to a burst length of the data.

公开(公告)号：US20170372764A1

公开(公告)日：2017-12-28

申请号：US15486689

申请日：2017-04-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SUNG-OH AHN ,  Sukyong Kang ,  Hye-Seung Yu ,  Jae-Hun Jung

IPC: G11C11/16 ,  G06F11/10 ,  G11C11/4076 ,  G11C13/00

CPC classification number: G11C11/1693 ,  G06F11/1004 ,  G11C7/1087 ,  G11C7/1093 ,  G11C7/222 ,  G11C11/161 ,  G11C11/4076 ,  G11C11/4093 ,  G11C13/0007 ,  G11C13/004 ,  G11C13/0061 ,  G11C13/0069

Abstract: A delay circuit of a semiconductor memory device includes a delay chain, a first phase converter and a second phase converter. The delay chain is connected between an input terminal and an output terminal, includes 2N delay cells, and delays a first intermediate signal to generate a second intermediate signal. The first phase converter is connected to the input terminal, and provides the first intermediate signal to the delay chain, wherein the first intermediate signal is generated by inverting a phase of an input signal or by maintaining the phase of the input signal in response to a control signal. The second phase converter is connected to the output terminal, and generates an output signal by inverting a phase of the second intermediate signal or by maintaining the phase of the second intermediate signal in response to the control signal.

公开(公告)号：US10938416B2

公开(公告)日：2021-03-02

申请号：US16262127

申请日：2019-01-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hye-Seung Yu ,  Sukyong Kang ,  Wonjoo Yun ,  Hyunui Lee ,  Jae-Hun Jung

IPC: H03M13/00 ,  H03M13/09 ,  G11C29/52 ,  G06F11/10

Abstract: A memory device including a parity check circuit and a mask circuit may be provided. The parity check circuit may perform parity check on data sampled according to a data strobe signal, which does not include a post-amble. The mask circuit may generate a parity error signal based on results of the parity check, and output the parity error signal during a time period determined according to a burst length of the data.

公开(公告)号：US20190140628A1

公开(公告)日：2019-05-09

申请号：US16026145

申请日：2018-07-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： WANGSOO KIM ,  Hangi Jung ,  Kiduk Park ,  Yoo-Chang Sung ,  Jae-Hun Jung ,  Cheongryong Cho ,  Hun-dae Choi

IPC: H03K5/13

CPC classification number: H03K5/13 ,  H03K2005/00019 ,  H04B1/04

Abstract: An electronic circuit may include a driver, a delay circuit, a strength control circuit, and an adder circuit. The driver may generate a second signal based on a first signal. The delay circuit may delay the first signal by as much as a reference time, to generate a third signal. The strength control circuit may adjust an amplitude of the third signal to generate a fourth signal. The adder circuit may add the second signal and the fourth signal to generate a fifth signal. In a first time interval determined based on the reference time, an amplitude of the fifth signal may be greater than an amplitude of the second signal. In a second time interval except for the first time interval, the amplitude of the fifth signal may be smaller than the amplitude of the second signal. In the second time interval, the amplitude of the fifth signal may be smaller than an amplitude of the first signal.

公开(公告)号：US10367490B2

公开(公告)日：2019-07-30

申请号：US16026145

申请日：2018-07-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Wangsoo Kim ,  Hangi Jung ,  Kiduk Park ,  Yoo-Chang Sung ,  Jae-Hun Jung ,  Cheongryong Cho ,  Hun-Dae Choi

IPC: H03K5/13 ,  H04B1/04 ,  H03K5/00

Abstract: An electronic circuit may include a driver, a delay circuit, a strength control circuit, and an adder circuit. The driver may generate a second signal based on a first signal. The delay circuit may delay the first signal by as much as a reference time, to generate a third signal. The strength control circuit may adjust an amplitude of the third signal to generate a fourth signal. The adder circuit may add the second signal and the fourth signal to generate a fifth signal. In a first time interval determined based on the reference time, an amplitude of the fifth signal may be greater than an amplitude of the second signal. In a second time interval except for the first time interval, the amplitude of the fifth signal may be smaller than the amplitude of the second signal. In the second time interval, the amplitude of the fifth signal may be smaller than an amplitude of the first signal.

公开(公告)号：US09966126B2

公开(公告)日：2018-05-08

申请号：US15486689

申请日：2017-04-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sung-Oh Ahn ,  Sukyong Kang ,  Hye-Seung Yu ,  Jae-Hun Jung

IPC: G11C11/00 ,  G11C11/16 ,  G11C11/4076 ,  G11C13/00 ,  G06F11/10

CPC classification number: G11C11/1693 ,  G06F11/1004 ,  G11C7/1087 ,  G11C7/1093 ,  G11C7/222 ,  G11C11/161 ,  G11C11/4076 ,  G11C11/4093 ,  G11C13/0007 ,  G11C13/004 ,  G11C13/0061 ,  G11C13/0069

Abstract: A delay circuit of a semiconductor memory device includes a delay chain, a first phase converter and a second phase converter. The delay chain is connected between an input terminal and an output terminal, includes 2N delay cells, and delays a first intermediate signal to generate a second intermediate signal. The first phase converter is connected to the input terminal, and provides the first intermediate signal to the delay chain, wherein the first intermediate signal is generated by inverting a phase of an input signal or by maintaining the phase of the input signal in response to a control signal. The second phase converter is connected to the output terminal, and generates an output signal by inverting a phase of the second intermediate signal or by maintaining the phase of the second intermediate signal in response to the control signal.

公开(公告)号：US09959935B2

公开(公告)日：2018-05-01

申请号：US15480724

申请日：2017-04-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sukyong Kang ,  Won-Joo Yun ,  Hye-Seung Yu ,  Hyun-Ui Lee ,  Jae-Hun Jung

IPC: G11C29/12 ,  G11C11/4076 ,  G11C11/4096

CPC classification number: G11C29/12 ,  G11C7/1087 ,  G11C11/4076 ,  G11C11/4093 ,  G11C11/4096 ,  G11C29/022 ,  G11C29/023 ,  G11C29/028 ,  G11C29/1201 ,  G11C29/12015 ,  G11C29/46 ,  G11C2029/1208

Abstract: An input-output circuit includes a reception circuit and a register circuit. The reception circuit operates in accordance with a normal write protocol commonly in a normal write mode and a test write mode. The reception circuit receives a plurality of input signals to generate a plurality of latch signals. The register circuit generates a plurality of test result signals based on the latch signals in the test write mode. The input-output circuit may perform the multiple-input shift register (MISR) function in accordance with the normal write path and the normal write protocol. The MISR function may be performed efficiently without consideration of additional timing adjustment for the test write operation because the MISR function is performed under the same timing condition as the normal write operation.