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公开(公告)号：US09870808B2
公开(公告)日：2018-01-16
申请号：US15295571
申请日：2016-10-17
发明人： Hyunui Lee , Won-joo Yun , Hye-seung Yu , In-dal Song
CPC分类号： G11C7/12 , G06F3/0608 , G06F3/0652 , G06F3/0656 , G06F3/0673 , G06F13/4086 , G11C7/02 , G11C7/1057 , G11C7/1084 , G11C7/22 , G11C8/08 , G11C8/14 , G11C29/021 , G11C29/022 , G11C29/028 , G11C29/12 , G11C29/12005 , G11C29/1201 , G11C29/56012 , G11C2029/5602 , G11C2207/105
摘要： Provided is a memory device configured to perform a calibration operation without having a ZQ pin. The memory device includes a calibration circuit configured to generate a pull-up calibration code and a pull-down calibration code which termination of a data input/output pad for impedance matching in the data input/output pad is controlled. The calibration circuit performs a first calibration operation for trimming first and second reference resistors based on an external resistor to be connected to a pad, and a second calibration operation for generating the pull-up calibration code and the pull-down calibration code based on the trimmed second reference resistor.
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公开(公告)号：US10938416B2
公开(公告)日：2021-03-02
申请号：US16262127
申请日：2019-01-30
发明人： Hye-Seung Yu , Sukyong Kang , Wonjoo Yun , Hyunui Lee , Jae-Hun Jung
摘要： A memory device including a parity check circuit and a mask circuit may be provided. The parity check circuit may perform parity check on data sampled according to a data strobe signal, which does not include a post-amble. The mask circuit may generate a parity error signal based on results of the parity check, and output the parity error signal during a time period determined according to a burst length of the data.
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公开(公告)号：US20190271742A1
公开(公告)日：2019-09-05
申请号：US16169107
申请日：2018-10-24
发明人： Hyunui Lee , Hye-Seung Yu , Won-Joo Yun
IPC分类号： G01R31/317 , G01R31/3177 , G11C29/02
摘要： A semiconductor memory device includes first bumps positioned along a first direction; second bumps positioned in parallel to the first bumps along the first direction; first registers connected with the first bumps; and second registers connected with the second bumps. The first registers and the second registers are sequentially connected and form a shift register.
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公开(公告)号：US10509070B2
公开(公告)日：2019-12-17
申请号：US16106127
申请日：2018-08-21
发明人： Won-Joo Yun , Sukyong Kang , Hye-Seung Yu , Hyunui Lee
IPC分类号： G01R31/28 , G01R31/02 , G01R31/26 , H01L21/66 , H01L25/065 , H03K17/687 , G11C29/00 , G11C29/02 , G11C29/50 , G11C5/02
摘要： Disclosed are a method and a device for detecting a short circuit between adjacent micro-bumps. The method includes setting outputs of a pull-up driver and a pull-down driver of a data output circuit connected with a micro-bump to be suitable for a test type and determining whether a short circuit is generated.
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公开(公告)号：US20180356458A1
公开(公告)日：2018-12-13
申请号：US16106127
申请日：2018-08-21
发明人： Won-Joo YUN , Sukyong Kang , Hye-Seung Yu , Hyunui Lee
IPC分类号： G01R31/28 , H03K17/687 , H01L21/66 , G01R31/26 , G11C29/00 , G11C29/02 , G11C29/50 , G01R31/02 , H01L25/065 , G11C5/02
摘要： Disclosed are a method and a device for detecting a short circuit between adjacent micro-bumps. The method includes setting outputs of a pull-up driver and a pull-down driver of a data output circuit connected with a micro-bump to be suitable for a test type and determining whether a short circuit is generated.
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公开(公告)号：US10908212B2
公开(公告)日：2021-02-02
申请号：US16169107
申请日：2018-10-24
发明人： Hyunui Lee , Hye-Seung Yu , Won-Joo Yun
IPC分类号： G01R31/00 , G01R31/317 , G11C29/02 , G01R31/3177
摘要： A semiconductor memory device includes first bumps positioned along a first direction; second bumps positioned in parallel to the first bumps along the first direction; first registers connected with the first bumps; and second registers connected with the second bumps. The first registers and the second registers are sequentially connected and form a shift register.
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公开(公告)号：US10243584B2
公开(公告)日：2019-03-26
申请号：US15488789
申请日：2017-04-17
发明人： Hye-Seung Yu , Sukyong Kang , Wonjoo Yun , Hyunui Lee , Jae-Hun Jung
摘要： A memory device including a parity check circuit and a mask circuit may be provided. The parity check circuit may perform parity check on data sampled according to a data strobe signal, which does not include a post-amble. The mask circuit may generate a parity error signal based on results of the parity check, and output the parity error signal during a time period determined according to a burst length of the data.
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公开(公告)号：US10078110B2
公开(公告)日：2018-09-18
申请号：US15295244
申请日：2016-10-17
发明人： Won-Joo Yun , Sukyong Kang , Hye-Seung Yu , Hyunui Lee
IPC分类号： G01R31/02 , G01R31/26 , G01R31/28 , H01L21/66 , H01L25/065 , H03K17/687 , G11C29/00 , G11C29/02 , G11C29/50 , G11C5/02
CPC分类号： G01R31/2853 , G01R31/025 , G01R31/26 , G01R31/2884 , G11C5/025 , G11C29/006 , G11C29/025 , G11C29/50008 , H01L22/14 , H01L22/34 , H01L25/0657 , H01L2224/16227 , H01L2225/06513 , H01L2225/06596 , H01L2924/15311 , H03K17/6872
摘要： Disclosed are a method and a device for detecting a short circuit between adjacent micro-bumps. The method includes setting outputs of a pull-up driver and a pull-down driver of a data output circuit connected with a micro-bump to be suitable for a test type and determining whether a short circuit is generated.
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