公开(公告)号：US20190221663A1

公开(公告)日：2019-07-18

申请号：US16367813

申请日：2019-03-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seok-Hoon KIM ,  Bon-Young KOO ,  Nam-Kyu KIM ,  Woo-Bin SONG ,  Byeong-Chan LEE ,  Su-Jin JUNG

IPC: H01L29/78 ,  H01L27/12 ,  H01L29/66 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/08

Abstract: A semiconductor device may include first and second fins formed side by side on a substrate, a first elevated doped region formed on the first fin and having a first doping concentration of impurities, a second elevated doped region formed on the second fin, and a first bridge connecting the first elevated doped region and the second elevated doped region to each other. Methods of manufacturing such a semiconductor device are also disclosed.

公开(公告)号：US20170117406A1

公开(公告)日：2017-04-27

申请号：US15398788

申请日：2017-01-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seok-Hoon KIM ,  Bon-Young KOO ,  Nam-Kyu KIM ,  Woo-Bin SONG ,  Byeong-Chan LEE ,  Su-Jin JUNG

IPC: H01L29/78 ,  H01L27/088 ,  H01L29/08 ,  H01L29/66

CPC classification number: H01L29/785 ,  H01L21/823431 ,  H01L27/0886 ,  H01L27/1211 ,  H01L29/0847 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/6681

Abstract: A semiconductor device may include first and second fins formed side by side on a substrate, a first elevated doped region formed on the first fin and having a first doping concentration of impurities, a second elevated doped region formed on the second fin, and a first bridge connecting the first elevated doped region and the second elevated doped region to each other. Methods of manufacturing such a semiconductor device are also disclosed.

公开(公告)号：US20140027824A1

公开(公告)日：2014-01-30

申请号：US13921616

申请日：2013-06-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Keum-Seok PARK ,  Jung-Ho YOO ,  Woo-Bin SONG ,  Byeong-Chan LEE

IPC: H01L29/78

CPC classification number: H01L29/78 ,  H01L21/823814 ,  H01L29/0684 ,  H01L29/165 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7848

Abstract: In a semiconductor device and a method of manufacturing the same, the semiconductor device includes a gate structure crossing an active region of a silicon substrate. Spacers are provided on both sides of the gate structure, respectively. Silicon patterns fill up recessed portions of the silicon substrate and on both sides of the spacers and has a shape protruding higher than a bottom surface of the gate structure, a lower edge of the protruded portion partially makes contact with a top surface of the isolation region, a first side and a second side of each of the silicon patterns, which are opposite to each other in a channel width direction in the gate structure, are inclined toward an inside of the active region. A highly doped impurity region is provided in the silicon patterns and doped with an N type impurity. The semiconductor device represents superior threshold voltage characteristics.

Abstract translation: 在半导体器件及其制造方法中，半导体器件包括与硅衬底的有源区交叉的栅极结构。 分别设置在门结构的两侧。 硅图案填充硅衬底的凹陷部分并且在间隔物的两侧上并且具有高于栅极结构的底表面突出的形状，突出部分的下边缘部分地与隔离区域的顶表面接触 ，在栅极结构中的沟道宽度方向上彼此相对的每个硅图案的第一侧和第二侧朝向有源区域的内部倾斜。 在硅图案中提供高掺杂杂质区，并掺杂有N型杂质。 半导体器件表现出优异的阈值电压特性。