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    SEMICONDUCTOR DEVICES INCLUDING A FINFET
    2.
    发明申请
    SEMICONDUCTOR DEVICES INCLUDING A FINFET 有权
    包括FINFET的半导体器件

    公开(公告)号：US20160293750A1

    公开(公告)日：2016-10-06

    申请号：US15049859

    申请日：2016-02-22

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jin-Bum KIM ,  Nam Kyu KIM ,  Hyun-Ho NOH ,  Dong-Chan SUH ,  Byeong-Chan LEE ,  Su-Jin JUNG ,  Jin-Yeong JOE ,  Bon-Young KOO

    IPC: H01L29/78 ,  H01L29/06 ,  H01L29/16

    CPC classification number: H01L29/785 ,  H01L29/0649 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165 ,  H01L29/7848 ,  H01L29/7856

    Abstract: A semiconductor device includes an active fin structure extending in a first direction, the active fin structure including protruding portions divided by a recess, a plurality of gate structures extending in a second direction crossing the first direction and covering the protruding portions of the active fin structure, a first epitaxial pattern in a lower portion of the recess between the gate structures, a second epitaxial pattern on a portion of the first epitaxial pattern, the second epitaxial pattern contacting a sidewall of the recess, and a third epitaxial pattern on the first and second epitaxial patterns, the third epitaxial pattern filling the recess. The first epitaxial pattern includes a first impurity region having a first doping concentration, the second epitaxial pattern includes a second impurity region having a second doping concentration lower than the a first doping concentration, and the third epitaxial pattern includes a third impurity region having a third doping concentration higher than the second doping concentration. The semiconductor device may have good electrical characteristics.

    Abstract translation: 半导体器件包括沿第一方向延伸的有源鳍结构，所述有源鳍结构包括由凹部分隔的突出部分，沿与第一方向交叉的第二方向延伸并覆盖有源鳍结构的突出部分的多个栅极结构 ，在栅极结构之间的凹部的下部中的第一外延图案，在第一外延图案的一部分上的第二外延图案，第二外延图案接触凹槽的侧壁，以及在第一外延图案的第一和第二外延图案 第二外延图案，填充凹槽的第三外延图案。 第一外延图案包括具有第一掺杂浓度的第一杂质区，第二外延图案包括具有低于第一掺杂浓度的第二掺杂浓度的第二杂质区，并且第三外延图包括具有第三掺杂浓度的第三杂质区 掺杂浓度高于第二掺杂浓度。 半导体器件可具有良好的电特性。

    SEMICONDUCTOR DEVICES HAVING COMPOSITE SPACERS CONTAINING DIFFERENT DIELECTRIC MATERIALS
    4.
    发明申请
    SEMICONDUCTOR DEVICES HAVING COMPOSITE SPACERS CONTAINING DIFFERENT DIELECTRIC MATERIALS 有权
    具有包含不同介质材料的复合间隔物的半导体器件

    公开(公告)号：US20150162332A1

    公开(公告)日：2015-06-11

    申请号：US14543140

    申请日：2014-11-17

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jin-Bum KIM ,  Bon-Young KOO ,  Seok-Hoon KIM ,  Chul KIM ,  Kwan-Heum LEE ,  Byeong-Chan LEE ,  Su-Jin JUNG

    IPC: H01L27/088 ,  H01L29/78 ,  H01L29/06 ,  H01L29/161

    CPC classification number: H01L27/0886 ,  H01L29/0653 ,  H01L29/161 ,  H01L29/66545 ,  H01L29/785

    Abstract: An integrated circuit device includes an electrically conductive pattern on a substrate. This electrically conductive pattern may be a gate pattern of a field effect transistor. A first electrically insulating spacer is provided on a sidewall of the electrically conductive pattern. The first electrically insulating spacer includes a first lower spacer and a first upper spacer, which extends on the first lower spacer and has a side surface vertically aligned with a corresponding side surface of the first lower spacer. The first upper spacer has a greater dielectric constant relative to a dielectric constant of the first lower spacer. A pair of parallel channel regions may also be provided, which protrude from a surface of the substrate. The electrically conductive pattern may surround top and side surfaces of the pair of parallel channel regions.

    Abstract translation: 集成电路器件包括在衬底上的导电图案。 该导电图案可以是场效应晶体管的栅极图案。 第一电绝缘垫片设置在导电图案的侧壁上。 第一电绝缘间隔件包括第一下间隔件和第一上间隔件，其在第一下间隔件上延伸并且具有与第一下间隔件的对应侧表面垂直对准的侧表面。 第一上间隔物相对于第一下间隔物的介电常数具有更大的介电常数。 还可以设置一对平行的通道区域，其从衬底的表面突出。 导电图案可以围绕该对平行通道区域的顶表面和侧表面。

    SEMICONDUCTOR DEVICES (as amended)
    5.
    发明申请
    SEMICONDUCTOR DEVICES (as amended) 有权
    SEMICONDUCTOR DEVICES（经修订）

    公开(公告)号：US20140027824A1

    公开(公告)日：2014-01-30

    申请号：US13921616

    申请日：2013-06-19

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Keum-Seok PARK ,  Jung-Ho YOO ,  Woo-Bin SONG ,  Byeong-Chan LEE

    IPC: H01L29/78

    CPC classification number: H01L29/78 ,  H01L21/823814 ,  H01L29/0684 ,  H01L29/165 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7848

    Abstract: In a semiconductor device and a method of manufacturing the same, the semiconductor device includes a gate structure crossing an active region of a silicon substrate. Spacers are provided on both sides of the gate structure, respectively. Silicon patterns fill up recessed portions of the silicon substrate and on both sides of the spacers and has a shape protruding higher than a bottom surface of the gate structure, a lower edge of the protruded portion partially makes contact with a top surface of the isolation region, a first side and a second side of each of the silicon patterns, which are opposite to each other in a channel width direction in the gate structure, are inclined toward an inside of the active region. A highly doped impurity region is provided in the silicon patterns and doped with an N type impurity. The semiconductor device represents superior threshold voltage characteristics.

    Abstract translation: 在半导体器件及其制造方法中，半导体器件包括与硅衬底的有源区交叉的栅极结构。 分别设置在门结构的两侧。 硅图案填充硅衬底的凹陷部分并且在间隔物的两侧上并且具有高于栅极结构的底表面突出的形状，突出部分的下边缘部分地与隔离区域的顶表面接触 ，在栅极结构中的沟道宽度方向上彼此相对的每个硅图案的第一侧和第二侧朝向有源区域的内部倾斜。 在硅图案中提供高掺杂杂质区，并掺杂有N型杂质。 半导体器件表现出优异的阈值电压特性。

    Semiconductor Device and Method for Fabricating the Same
    7.
    发明申请
    Semiconductor Device and Method for Fabricating the Same 有权
    半导体器件及其制造方法

    公开(公告)号：US20140299934A1

    公开(公告)日：2014-10-09

    申请号：US14194837

    申请日：2014-03-03

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Seok-Hoon KIM ,  Tae-Ouk KWON ,  Su-Jin JUNG ,  Young-Pil KIM ,  Byeong-Chan LEE ,  Bon-Young KOO

    IPC: H01L29/78

    CPC classification number: H01L29/7848 ,  H01L29/66545 ,  H01L29/785

    Abstract: Provided is a semiconductor device. The semiconductor device includes a fin on a substrate; a gate electrode cross the fin on the substrate; a source/drain formed on at least one of both sides of the gate electrode, and including a first film and a second film; and a stress film arranged between an isolation film on the substrate and the source/drain, and formed on a side surface of the fin.

    Abstract translation: 提供一种半导体器件。 半导体器件在衬底上包括翅片; 栅电极跨越衬底上的翅片; 源极/漏极，形成在栅电极的两侧中的至少一个上，并且包括第一膜和第二膜; 以及布置在基板上的隔离膜和源极/漏极之间并且形成在鳍的侧表面上的应力膜。

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