公开(公告)号：US20190355728A1

公开(公告)日：2019-11-21

申请号：US16181510

申请日：2018-11-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dong-oh Kim ,  Ki-seok Lee ,  Chan-sic Yoon ,  Je-min Park ,  Woo-song Ahn

IPC: H01L27/108 ,  H01L23/538 ,  H01L29/49

Abstract: An integrated circuit device includes: a substrate having a cell array area, which includes a first active region, and a peripheral circuit area, which includes a second active region; a direct contact connected to the first active region in the cell array area; a bit line structure connected to the direct contact in the cell array area; and a peripheral circuit gate structure on the second active region in the peripheral circuit area, wherein the peripheral circuit gate structure includes two doped semiconductor layers each being doped with a charge carrier impurity having different doping concentrations from each other.

公开(公告)号：US10784266B2

公开(公告)日：2020-09-22

申请号：US16181510

申请日：2018-11-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dong-oh Kim ,  Ki-seok Lee ,  Chan-sic Yoon ,  Je-min Park ,  Woo-song Ahn

IPC: H01L27/108 ,  H01L23/538 ,  H01L29/49 ,  H01L21/265 ,  H01L21/28 ,  H01L21/285 ,  H01L21/308 ,  H01L29/66

Abstract: An integrated circuit device includes: a substrate having a cell array area, which includes a first active region, and a peripheral circuit area, which includes a second active region; a direct contact connected to the first active region in the cell array area; a bit line structure connected to the direct contact in the cell array area; and a peripheral circuit gate structure on the second active region in the peripheral circuit area, wherein the peripheral circuit gate structure includes two doped semiconductor layers each being doped with a charge carrier impurity having different doping concentrations from each other.