公开(公告)号：US20210036121A1

公开(公告)日：2021-02-04

申请号：US16822275

申请日：2020-03-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kangmook Lim ,  Sangsu Kim ,  Wooseok Park ,  Daekwon Joo

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L27/088

Abstract: A semiconductor device is provided including an active region on a substrate A plurality of channel layers is spaced apart on the active region. Gate structures are provided. The gate structures intersect the active region and the plurality of channel layers. The gate structures surround the plurality of channel layers. Source/drain regions are disposed on the active region on at least one side of the gate structures. The source/drain regions contact with the plurality of channel layers. A lower insulating layer is disposed between side surfaces of the gate structures on the source/drain regions. Contact plugs penetrate through the lower insulating layer. The contact plugs contact the source/drain regions. An isolation structure intersects the active region on the substrate and is disposed between the source/drain regions adjacent to each other. Each of the gate structures includes a gate electrode and a gate capping layer including materials different from each other.

公开(公告)号：US20240379409A1

公开(公告)日：2024-11-14

申请号：US18535089

申请日：2023-12-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaeho Jeon ,  Wooseok Park ,  Donghoon Hwang ,  Myungil Kang ,  Kyungho Kim ,  Byungho Moon

IPC: H01L21/762 ,  H01L23/522 ,  H01L23/528 ,  H01L29/06 ,  H01L29/66

Abstract: A semiconductor device includes a substrate including an active pattern that is defined by a trench, a device isolation layer in the trench, a first source/drain pattern and a second source/drain pattern on the active pattern, a partition wall between the first and second source/drain patterns, a dam structure and a gate cutting pattern on the device isolation layer, and a gate spacer on a side surface of the gate cutting pattern. The first source/drain pattern is in a recess between the partition wall and the dam structure, and a lower portion of the gate spacer is interposed between the dam structure and the gate cutting pattern. A first thickness of the lower portion of the gate spacer is different from a second thickness of an upper portion of the gate spacer.

公开(公告)号：US11901357B2

公开(公告)日：2024-02-13

申请号：US17380232

申请日：2021-07-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Junggun You ,  Sung Gi Hur ,  Sungil Park ,  Wooseok Park ,  Seungmin Song

IPC: H01L27/088

CPC classification number: H01L27/088

Abstract: A semiconductor device including a substrate that includes first and second regions; a first active pattern on the first region, the first active pattern including first source/drain patterns and a first channel pattern between the first source/drain patterns; a second active pattern on the second region, the second active pattern including second source/drain patterns and a second channel pattern between the second source/drain patterns; and a first gate electrode on the first channel pattern and a second gate electrode on the second channel pattern, wherein a length of the first channel pattern is greater than a length of the second channel pattern, each of the first channel pattern and the second channel pattern includes a plurality of semiconductor patterns stacked on the substrate, and at least two semiconductor patterns of the first channel pattern are bent away from or toward a bottom surface of the substrate.

公开(公告)号：US11195928B2

公开(公告)日：2021-12-07

申请号：US16822275

申请日：2020-03-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kangmook Lim ,  Sangsu Kim ,  Wooseok Park ,  Daekwon Joo

IPC: H01L29/423 ,  H01L27/088 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/762 ,  H01L21/306

Abstract: A semiconductor device is provided including an active region on a substrate A plurality of channel layers is spaced apart on the active region. Gate structures are provided. The gate structures intersect the active region and the plurality of channel layers. The gate structures surround the plurality of channel layers. Source/drain regions are disposed on the active region on at least one side of the gate structures. The source/drain regions contact with the plurality of channel layers. A lower insulating layer is disposed between side surfaces of the gate structures on the source/drain regions. Contact plugs penetrate through the lower insulating layer. The contact plugs contact the source/drain regions. An isolation structure intersects the active region on the substrate and is disposed between the source/drain regions adjacent to each other. Each of the gate structures includes a gate electrode and a gate capping layer including materials different from each other.