公开(公告)号：US20250169067A1

公开(公告)日：2025-05-22

申请号：US19028305

申请日：2025-01-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JAESAN KIM ,  SEUNGHAN WOO ,  HAESUK LEE ,  YOUNGCHEON KWON ,  REUM OH

IPC: H10B12/00 ,  H01L23/48 ,  H01L23/528 ,  H10D1/43 ,  H10D1/66

Abstract: A semiconductor device includes a semiconductor structure including a semiconductor substrate having an active zone with a channel; a through silicon via (TSV) structure including a power TSV configured to transmit power and a signal TSV configured to transmit a signal; and a keep-out zone located a predetermined distance away from the TSV structure and bounded by the active zone. The TSV structure penetrates the semiconductor substrate. The keep-out zone includes a first element area a first distance away from the power TSV, and a second element area a second distance away from the signal TSV.

公开(公告)号：US20220238148A1

公开(公告)日：2022-07-28

申请号：US17722494

申请日：2022-04-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： YOUNGCHEON KWON ,  SANGHYUK KWON ,  KYOMIN SOHN ,  JAEYOUN YOUN ,  HAESUK LEE

IPC: G11C11/406 ,  G11C11/408

Abstract: A memory device according to some aspects of the inventive concepts includes a memory cell array including a plurality of banks, at least one Processing Element (PE) connected to at least one bank selected from the plurality of banks, and a control logic configured to control an active operation in which wordlines included in each of the plurality of banks is activated, and configured to control a refresh operation in which at least one bank is refreshed, based on a PE enable signal configured to selectively enable the at least one PE.

公开(公告)号：US20210193615A1

公开(公告)日：2021-06-24

申请号：US16926189

申请日：2020-07-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： YOUNGCHEON KWON ,  KYOMIN SOHN ,  YAEYOUN YOUN

IPC: H01L25/065 ,  H01L23/538 ,  H01L21/66

Abstract: High bandwidth memories and systems including the same may include a buffer die, a plurality of memory dies stacked on the buffer die, a plurality of dummy bump groups in edge regions of the buffer die and the plurality of memory dies, and a plurality of signal line groups. Each of the plurality of dummy bump groups includes dummy bumps spaced apart from each other between each pair of adjacent dies and configured to connect the two adjacent dies to each other. Each of the signal line groups includes a plurality of signal lines configured to transmit a corresponding signal among an input signal and a plurality of bump crack detection signals applied to an input dummy bump of each of the plurality of dummy bump groups via sequential transmission through the plurality of dummy bumps to an output dummy bump during a bump crack test operation.