公开(公告)号：US11902092B2

公开(公告)日：2024-02-13

申请号：US16790582

申请日：2020-02-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Qinling Zheng ,  Ehsan Najafabadi ,  Yasser Zaghloul

IPC: H04L67/1008 ,  H04L41/0823 ,  G06N3/049 ,  H04L43/16 ,  H04L41/16 ,  G06F9/455 ,  H04L47/31

CPC classification number: H04L41/0823 ,  G06F9/45558 ,  G06N3/049 ,  H04L41/16 ,  H04L43/16 ,  H04L47/31 ,  H04L67/1008 ,  G06F2009/45591

Abstract: Provided are systems, methods, and apparatuses for latency-aware edge computing to optimize network traffic. A method can include: determining network parameters associated with a network architecture, the network architecture comprising a data center and an edge data center; determining, using the network parameters, a first programmatically expected latency associated with the data center and a second programmatically expected latency associated with the edge data center; and determining, based at least in part on a difference between the first programmatically expected latency or the second programmatically expected latency, a distribution of a workload to be routed between the data center and the edge data center.

公开(公告)号：US12125559B2

公开(公告)日：2024-10-22

申请号：US16551712

申请日：2019-08-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Salvatore Arcuri ,  Stephen Fischer ,  Vijay Balakrishnan ,  Anahita Shayesteh ,  Ramdas P. Kachare ,  Jason Martineau ,  Yasser Zaghloul

IPC: G16B30/10 ,  G06F3/06 ,  G16B50/30

CPC classification number: G16B30/10 ,  G06F3/061 ,  G06F3/0658 ,  G06F3/0679 ,  G16B50/30

Abstract: A field programmable gate array (FPGA) may: identify a continuous match of atoms between the search sequence and the reference sequence; divide the search sequence into a left portion of the search sequence that includes atoms before the continuous match of atoms in the search sequence, a center portion of the search sequence that includes the continuous match of atoms in the search sequence, and a right portion of the search sequence that includes atoms after the continuous match of atoms in the search sequence; match the left portion of the search sequence with the reference sequence; and match the right portion of the search sequence with the reference sequence.

公开(公告)号：US20210318815A1

公开(公告)日：2021-10-14

申请号：US16926636

申请日：2020-07-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sompong Paul Olarig ,  Yasser Zaghloul

IPC: G06F3/06

Abstract: A storage device may include a connector comprising a power management pin, a detector circuit configured to detect a transition of a power management signal received on the power management pin, and a power management circuit capable of configuring power to at least a portion of the storage device based, at least in part, on the detector circuit detecting a transition of the power management signal. The connector may further include a port enable pin, and the power management circuit may be configured to be disabled based, at least in part, on a state of the port enable pin. A storage device may include a connector comprising a power management pin, a nonvolatile memory, and a power management circuit configured to operate in a first power management mode based on determining a first state of the nonvolatile memory.

公开(公告)号：US11656770B2

公开(公告)日：2023-05-23

申请号：US16926636

申请日：2020-07-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sompong Paul Olarig ,  Yasser Zaghloul

IPC: G06F3/06

CPC classification number: G06F3/0625 ,  G06F3/0659 ,  G06F3/0679

Abstract: A storage device may include a connector comprising a power management pin, a detector circuit configured to detect a transition of a power management signal received on the power management pin, and a power management circuit capable of configuring power to at least a portion of the storage device based, at least in part, on the detector circuit detecting a transition of the power management signal. The connector may further include a port enable pin, and the power management circuit may be configured to be disabled based, at least in part, on a state of the port enable pin. A storage device may include a connector comprising a power management pin, a nonvolatile memory, and a power management circuit configured to operate in a first power management mode based on determining a first state of the nonvolatile memory.

公开(公告)号：US20200267053A1

公开(公告)日：2020-08-20

申请号：US16790582

申请日：2020-02-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Qinling Zheng ,  Ehsan Najafabadi ,  Yasser Zaghloul

IPC: H04L12/24 ,  G06N3/04 ,  H04L12/26 ,  H04L12/833 ,  H04L29/08 ,  G06F9/455

Abstract: Provided are systems, methods, and apparatuses for latency-aware edge computing to optimize network traffic. A method can include: determining network parameters associated with a network architecture, the network architecture comprising a data center and an edge data center; determining, using the network parameters, a first programmatically expected latency associated with the data center and a second programmatically expected latency associated with the edge data center; and determining, based at least in part on a difference between the first programmatically expected latency or the second programmatically expected latency, a distribution of a workload to be routed between the data center and the edge data center.