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    SYSTEMS AND METHODS FOR EXECUTING DATA PROCESSING FUNCTIONS
    3.
    发明公开
    SYSTEMS AND METHODS FOR EXECUTING DATA PROCESSING FUNCTIONS 审中-公开

    公开(公告)号：US20240086102A1

    公开(公告)日：2024-03-14

    申请号：US17960033

    申请日：2022-10-04

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Ramdas P. Kachare ,  Amir Beygi ,  Mostafa Aghaee ,  Jingchi Yang ,  Tinh Tri Lac ,  Sonny Pham ,  Nayankumar Patel

    IPC: G06F3/06 ,  G06F13/38

    CPC classification number: G06F3/0655 ,  G06F3/061 ,  G06F3/0683 ,  G06F13/385

    Abstract: Systems and methods for executing a data processing function are disclosed. A first processing device of a storage accelerator loads a first instruction set associated with a first application of a host computing device. A second processing device of the storage accelerator loads a second instruction set associated with the first application. A command is received from the host computing device. The command may be associated with data associated with the first application. The first processing device identifies at least a first criterion or a second criterion associated with the data. The first processing device processes the data according to the first instruction set in response to identifying the first criterion. The first processing device writes the data to a buffer of the second processing device in response to identifying the second criterion. The second processing device processes the data in the buffer according to the second instruction set.

    SYSTEMS, METHODS, AND DEVICES FOR KEY PER INPUT/OUTPUT SECURITY
    5.
    发明申请
    SYSTEMS, METHODS, AND DEVICES FOR KEY PER INPUT/OUTPUT SECURITY 有权

    公开(公告)号：US20230137282A1

    公开(公告)日：2023-05-04

    申请号：US18090110

    申请日：2022-12-28

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Ramdas P. Kachare ,  Xuebin Yao ,  Jimmy K. Lau

    IPC: H04L9/08 ,  G06F13/16 ,  G06F21/79

    Abstract: A device includes a communications circuit configured to communicate with a storage device controller and a host device. The device further includes a processing device configured to receive a request from the storage device controller through the communications circuit. The request requests encrypted data be written to a memory address of the host device. The processing device is further configured to identify a key associated with the write request based on the memory address. The processing device is further configured to generate a decrypted version of the data based on the key. The processing device is further configured to initiate transfer, through the communications circuit, of the decrypted version of the data to the host device.

    Efficient data movement method for in storage computation
    7.
    发明授权
    Efficient data movement method for in storage computation 有权

    公开(公告)号：US11243714B2

    公开(公告)日：2022-02-08

    申请号：US16509476

    申请日：2019-07-11

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Ramdas P. Kachare ,  Jimmy K. Lau

    IPC: G06F3/06 ,  G06F13/28 ,  G06F12/10

    Abstract: A Solid State Drive (SSD) is disclosed. The SSD may include flash memory storage to store data, a volatile memory storage, and a host interface layer to receive requests from a host machine. An SSD controller may manage reading data from and writing data to the flash memory storage, with a flash translation layer to translate between Logical Block Addresses and Physical Block Addresses, a flash memory controller to access the flash memory storage, a volatile memory controller to access the volatile memory storage, and an orchestrator to send instructions to a Data Movement Interconnect (DMI). The DMI may include at least two kernels, a Buffer Manager, a plurality of ring agents associated with the kernels and the Buffer Manager to handle messaging, a Data Movement Manager (DMM) to manage data movement, at least two data rings to move data between the ring agents, and a control ring to share commands and acknowledgments between the ring agents and the DMM.

    SSD architecture for FPGA based acceleration
    9.
    发明授权
    SSD architecture for FPGA based acceleration 有权

    公开(公告)号：US11100017B2

    公开(公告)日：2021-08-24

    申请号：US16752612

    申请日：2020-01-24

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Ramdas P. Kachare ,  Fred Worley ,  Harry Rogers ,  Wentao Wu ,  Nagarajan Subramaniyan

    IPC: G06F13/16 ,  G06F13/40 ,  G06F13/42

    Abstract: A system is disclosed. The system may include a processor running an application program and a memory storing data being used by the application program. An upstream interface enables communication with the processor; a downstream interface enables communication with a storage device. The system may also include an acceleration module implemented using hardware and including an Acceleration Platform Manager (APM-F) to execute an acceleration instruction. The storage device may include an endpoint of the storage device for communicating with the acceleration module, a controller to manage operations of the storage device, storage for application data for the application program, and a storage device Acceleration Platform Manager (APM-S) to assist the APM-F in executing the acceleration instruction. The processor, the acceleration module, and the storage device may communicate via a Peripheral Component Interconnect Exchange (PCIe) bus. The acceleration module may support performing the acceleration instruction on the application data on the storage device for the application program without loading the application data into the memory.

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