公开(公告)号：US20170162675A1

公开(公告)日：2017-06-08

申请号：US15361516

申请日：2016-11-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jun-Hwan YIM ,  Yeon-Tack RYU ,  Joo-Cheol HAN ,  Ja-Eung KOO ,  No-Ul KIM ,  Ho-Young KIM ,  Bo-Un YOON

IPC: H01L29/66 ,  H01L29/51 ,  H01L21/28 ,  H01L21/8238 ,  H01L29/49 ,  H01L21/3105 ,  H01L21/02

CPC classification number: H01L29/66795 ,  H01L21/0217 ,  H01L21/0228 ,  H01L21/28088 ,  H01L21/31051 ,  H01L21/31058 ,  H01L21/823821 ,  H01L21/823828 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545

Abstract: Disclosed is a method of manufacturing semiconductor devices. A gate trench and an insulation pattern defined by the gate trench are formed on a substrate and the protection pattern is formed on the insulation pattern. A gate dielectric layer, a work function metal layer and a sacrificial layer are sequentially formed the substrate along a surface profile of the gate trench. A sacrificial pattern is formed by a CMP while not exposing the insulation pattern. A residual sacrificial pattern is formed at a lower portion of the gate trench and the gate dielectric layer and the work function metal layer is etched into a gate dielectric pattern and a work function metal pattern using the residual sacrificial pattern as an etch stop layer.

公开(公告)号：US20160104788A1

公开(公告)日：2016-04-14

申请号：US14815225

申请日：2015-07-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yeon-Tack RYU ,  Ho-Young KIM ,  Myoung-Hwan OH ,  Bo-Un YOON ,  Jun-Hwan YIM

IPC: H01L29/66 ,  H01L29/40 ,  H01L21/283

CPC classification number: H01L29/66545 ,  H01L21/31053 ,  H01L21/76829 ,  H01L21/76834 ,  H01L21/76897 ,  H01L21/823437 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517

Abstract: Semiconductor devices and methods of fabricating semiconductor devices are provided. The methods may include forming an interlayer insulation layer on a substrate. The interlayer insulation layer may surround a dummy silicon gate and may expose a top surface of the dummy silicon gate. The methods may also include recessing a portion of the interlayer insulation layer such that a portion of the dummy silicon gate protrudes above a top surface of the recessed interlayer insulation layer and forming an etch stop layer on the recessed interlayer insulation layer. A top surface of the etch stop layer may be coplanarly positioned with the top surface of the dummy silicon gate. The methods may further include forming a trench exposing the substrate by removing the dummy silicon gate using the etch stop layer as a mask.

Abstract translation: 提供了制造半导体器件的半导体器件和方法。 所述方法可以包括在基底上形成层间绝缘层。 层间绝缘层可以包围虚拟硅栅极并且可以暴露虚拟硅栅极的顶表面。 所述方法还可以包括使所述层间绝缘层的一部分凹陷，使得所述虚拟硅栅极的一部分突出于所述凹陷层间绝缘层的顶表面之上，并在所述凹陷层间绝缘层上形成蚀刻停止层。 蚀刻停止层的顶表面可以与虚拟硅栅极的顶表面共面定位。 所述方法还可以包括通过使用蚀刻停止层作为掩模去除伪硅栅极来形成暴露衬底的沟槽。