公开(公告)号：US20170278746A1

公开(公告)日：2017-09-28

申请号：US15292756

申请日：2016-10-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yong-Kong SIEW

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L21/76823 ,  H01L21/288 ,  H01L21/76808 ,  H01L21/7681 ,  H01L21/76831 ,  H01L21/76835 ,  H01L21/76846 ,  H01L21/76849 ,  H01L21/76877 ,  H01L21/76879 ,  H01L21/76885 ,  H01L21/76897 ,  H01L21/823431 ,  H01L21/823475 ,  H01L23/5226 ,  H01L23/53209 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53252

Abstract: In a method of manufacturing a semiconductor device, a first insulating interlayer and a sacrificial layer is sequentially formed on a substrate. The sacrificial layer is partially removed to form a first opening exposing an upper surface of the first insulating interlayer. An insulating liner including silicon oxide is conformally formed on the exposed upper surface of the first insulating interlayer and a sidewall of the first opening. At least a portion of the insulating liner on the upper surface of the first insulating interlayer and a portion of the first insulating interlayer thereunder are removed to form a second opening connected to the first opening. A self-forming barrier (SFB) pattern is formed on a sidewall of the second opening and the insulating liner. A wiring structure is formed to fill the first and second openings. After the sacrificial layer is removed, a second insulating interlayer is formed.

公开(公告)号：US20160372415A1

公开(公告)日：2016-12-22

申请号：US15015296

申请日：2016-02-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yong-Kong SIEW ,  Sang-Hoon AHN

IPC: H01L23/528 ,  H01L29/06 ,  H01L23/522 ,  H01L23/532 ,  H01L27/088

CPC classification number: H01L27/0886 ,  H01L21/76264 ,  H01L21/76289 ,  H01L21/76811 ,  H01L21/7682 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76849 ,  H01L21/76897 ,  H01L23/4821 ,  H01L23/5222 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/5329 ,  H01L23/53295 ,  H01L29/41783 ,  H01L29/665 ,  H01L29/66545

Abstract: A semiconductor device may include a plurality of wiring structures spaced apart from each other, a protection pattern including a metal nitride on each of the wiring structures, a spacer on a sidewall of the protection pattern, and an insulating interlayer structure containing the wiring structures and having an air gap between the wiring structures.

Abstract translation: 半导体器件可以包括彼此间隔开的多个布线结构，在每个布线结构上包括金属氮化物的保护图案，保护图案的侧壁上的间隔物和包含布线结构的绝缘夹层结构， 在布线结构之间具有气隙。