公开(公告)号：US20220004852A1

公开(公告)日：2022-01-06

申请号：US17150891

申请日：2021-01-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yongmin JU ,  Sangjoon KIM ,  Hyungwoo LEE ,  Seungchul JUNG

IPC: G06N3/063 ,  G06N3/04 ,  G11C11/4076 ,  G11C11/4074

Abstract: An in-memory processing apparatus includes: a memory cell array comprising memory cell groups configured to generate current sums of column currents flowing through respective column lines in response to input signals input through row lines; voltage controlled delay circuits configured to output, in response to an input of a start signal at a first time point, stop signals at second time points delayed by delay times determined based on magnitudes of applied sampling voltages corresponding to the current sums; and a time-digital converter configured to perform time-digital conversion at the second time points.

公开(公告)号：US20230078279A1

公开(公告)日：2023-03-16

申请号：US17992143

申请日：2022-11-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyungwoo LEE ,  Sangjoon KIM ,  Yongmin JU

IPC: G11C13/00 ,  G06N3/063 ,  G11C11/54

Abstract: An apparatus for performing in-memory processing includes a memory cell array of memory cells configured to output a current sum of a column current flowing in respective column lines of the memory cell array based on an input signal applied to row lines of the memory cells, a sampling circuit, comprising a capacitor connected to each of the column lines, configured to be charged by a sampling voltage of a corresponding current sum of the column lines, and a processing circuit configured to compare a reference voltage and a currently charged voltage in the capacitor in response to a trigger pulse generated at a timing corresponding to a quantization level, among quantization levels, time-sectioned based on a charge time of the capacitor, and determine the quantization level corresponding to the sampling voltage by performing time-digital conversion when the currently charged voltage reaches the reference voltage.

公开(公告)号：US20220114427A1

公开(公告)日：2022-04-14

申请号：US17238403

申请日：2021-04-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seungchul JUNG ,  Hyungwoo LEE ,  Sungmeen MYUNG ,  Yongmin JU

IPC: G06N3/063 ,  G06F7/544

Abstract: A neural network apparatus includes: a plurality of memory cells each comprising a variable resistance element and a first transistor; a plurality of bit lines extending in a first direction; and a plurality of word lines extending in a second direction, crossing the bit lines and respectively connected to the first transistor of the plurality of memory cells; a plurality of sub-column circuits each comprising memory cells of the memory cells connected in parallel along the first direction; and a column circuit comprising two or more of the sub-column circuits connected in series along the second direction, wherein, when a neural network operation is performed, the column circuit outputs a summation current to a bit line connected to the column circuit based on voltage applied to the plurality of word lines.

公开(公告)号：US20230046817A1

公开(公告)日：2023-02-16

申请号：US17974852

申请日：2022-10-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yongmin JU ,  Sangjoon KIM ,  Hyungwoo LEE ,  Seungchul JUNG

IPC: G11C11/54 ,  G11C11/4074 ,  G11C11/4076 ,  G11C11/4091

Abstract: An in-memory processing apparatus includes: a memory cell array comprising memory cell groups configured to generate current sums of column currents flowing through respective column lines in response to input signals input through row lines; voltage controlled delay circuits configured to output, in response to an input of a start signal at a first time point, stop signals at second time points delayed by delay times determined based on magnitudes of applied sampling voltages corresponding to the current sums; a time-digital converter configured to perform time-digital conversion at the second time points; and sampling resistors connected to the column lines, wherein the time-digital converter is configured to reset a counter at the first time point, and output counting values as digital values at the second time points.

公开(公告)号：US20210366542A1

公开(公告)日：2021-11-25

申请号：US17141474

申请日：2021-01-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyungwoo LEE ,  Sangjoon KIM ,  Yongmin JU

IPC: G11C13/00

Abstract: An apparatus for performing in-memory processing includes a memory cell array of memory cells configured to output a current sum of a column current flowing in respective column lines of the memory cell array based on an input signal applied to row lines of the memory cells, a sampling circuit, comprising a capacitor connected to each of the column lines, configured to be charged by a sampling voltage of a corresponding current sum of the column lines, and a processing circuit configured to compare a reference voltage and a currently charged voltage in the capacitor in response to a trigger pulse generated at a timing corresponding to a quantization level, among quantization levels, time-sectioned based on a charge time of the capacitor, and determine the quantization level corresponding to the sampling voltage by performing time-digital conversion when the currently charged voltage reaches the reference voltage.