公开(公告)号：US20220019885A1

公开(公告)日：2022-01-20

申请号：US17195917

申请日：2021-03-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seungchul JUNG ,  Sangjoon KIM ,  Sungmeen MYUNG

IPC: G06N3/063 ,  H01L27/22 ,  G06F7/544

Abstract: A processing device includes: a plurality of bitcells, each of the plurality of bitcells including: a variable resistor layer including a plurality of active variable resistors and a plurality of inactive variable resistors; an active layer including a plurality of switches configured to control either one of a voltage to be applied between ends of each of the active variable resistors and a current flowing to each of the active variable resistors; and a plurality of metal layers including wires electrically connecting the active variable resistors to the switches, wherein at least one of the plurality of bitcells includes a via penetrating through the variable resistor layer and connecting at least one of the switches to at least one of the active variable resistors.

公开(公告)号：US20250166702A1

公开(公告)日：2025-05-22

申请号：US18947724

申请日：2024-11-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jaehyuk LEE ,  Soon-Wan KWON ,  Sang Joon KIM ,  Sungmeen MYUNG ,  Boyoung SEO ,  Seok Ju YUN ,  Kangho LEE

IPC: G11C13/00

Abstract: A non-volatile memory device includes a memory array including N+1 resistive memory cells expressing a bit sequence of N bits for each word line, in which N is an integer greater than or equal to 2.

公开(公告)号：US20250094127A1

公开(公告)日：2025-03-20

申请号：US18969509

申请日：2024-12-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seungchul JUNG ,  Sang Joon KIM ,  Sungmeen MYUNG ,  Seok Ju YUN ,  Seungkeun YOON

IPC: G06F7/544 ,  H03K3/037 ,  H03K21/08

Abstract: A computing device for performing a digital pulse-based crossbar operation and a method of operating the computing device. The computing device includes a plurality of input lines to which a pulse is selectively input in a sequential manner based on a corresponding input signal; a plurality of output lines crossing the input lines; a plurality of elements, each element being disposed at a cross point between a corresponding input line and a corresponding output line to transfer, to the corresponding output line, a pulse input to the corresponding input line in response to a corresponding weight being a first value; and a plurality of pulse counters, each pulse counter counting a number of pulses output from a corresponding output line.

公开(公告)号：US20240069867A1

公开(公告)日：2024-02-29

申请号：US18351039

申请日：2023-07-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seok Ju YUN ,  Jaehyuk LEE ,  Seungchul JUNG ,  Soon-Wan KWON ,  Sungmeen MYUNG ,  Daekun YOON ,  Dong-Jin CHANG

IPC: G06F7/523 ,  G06F7/501 ,  G06F7/544 ,  G11C7/10

CPC classification number: G06F7/523 ,  G06F7/501 ,  G06F7/5443 ,  G11C7/109

Abstract: An apparatus and method with in-memory computing (IMC) are provided. An in-memory computing (IMC) circuit includes a plurality of memory banks, each memory bank including a bit cell configured to store a weight value and an operator configured to receive an input value, the operator being connected to the bit cell such that the operator upon receiving the input value outputs a logic operation result between the input value and the weight value, and a logic gate configured to receive the logic operation result of each of the memory banks.

公开(公告)号：US20240354059A1

公开(公告)日：2024-10-24

申请号：US18761402

申请日：2024-07-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sungmeen MYUNG ,  Sangjoon KIM ,  Seungchul JUNG

IPC: G06F7/544 ,  G01R19/00 ,  G06F13/40 ,  G06F13/42 ,  G06N3/04 ,  G11C11/16 ,  G11C11/54

CPC classification number: G06F7/5443 ,  G01R19/0046 ,  G06F13/4022 ,  G06F13/4282 ,  G06N3/04 ,  G11C11/161 ,  G11C11/1673 ,  G11C11/54

Abstract: A neuromorphic device includes a plurality of resistor lines, each comprising a plurality of resistors that are serially connected to each other; one or more current sources configured to control a current flowing in each of the resistor lines to a respective current value; a plurality of capacitors configured to be electrically connected to each of the resistor lines and to sample respective voltage of each of the resistor lines representing results of neuromorphic operations; and a switch configured to connect the plurality of the capacitors in parallel after the sampling the respective voltage of each of the resistor lines, to output a sum of the results of neuromorphic operations.

公开(公告)号：US20240094988A1

公开(公告)日：2024-03-21

申请号：US18117597

申请日：2023-03-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dong-Jin CHANG ,  Sungmeen MYUNG ,  Jaehyuk LEE ,  Daekun YOON ,  Seok Ju YUN

IPC: G06F7/544 ,  G06F7/40

CPC classification number: G06F7/5443 ,  G06F7/405

Abstract: A multi-bit accumulator including a plurality of 1-bit Wallace trees configured to perform an add operation on single-bit input data, a plurality of tristate buffers configured to output a result of the add operation of the 1-bit Wallace trees, according to an enable signal, and a shift-adder configured to perform an accumulation operation on the result of the add operation of the plurality of 1-bit Wallace trees by a shift operation based on a clock signal.

公开(公告)号：US20240028298A1

公开(公告)日：2024-01-25

申请号：US18185461

申请日：2023-03-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jaehyuk LEE ,  Seok Ju YUN ,  Dong-Jin CHANG ,  Sungmeen MYUNG ,  Daekun YOON

IPC: G06F7/544 ,  G11C11/412 ,  G11C11/418 ,  G11C11/419

CPC classification number: G06F7/5443 ,  G11C11/412 ,  G11C11/418 ,  G11C11/419

Abstract: A memory device performs a multiplication operation using a multiplying cell including a memory cell and a switching element, in which the memory cell includes a pair of inverters connected to each other in opposite directions, a first transistor connected to one end of the pair of inverters, and a second transistor connected to the other end of the pair of inverters, and has a set weight; and the switching element is connected to an output end of the memory cell and configured to perform switching in response to an input value and output a signal corresponding to a multiplication result between the input value and the weight.

公开(公告)号：US20250013714A1

公开(公告)日：2025-01-09

申请号：US18764855

申请日：2024-07-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaehyuk LEE ,  Dong-Jin CHANG ,  Sungmeen MYUNG ,  Daekun YOON ,  Seok Ju YUN

IPC: G06F17/15

Abstract: A processor-implemented method includes receiving an input vector comprising a plurality of channels, performing a first convolution operation by allocating first chunks, obtained by dividing the input vector, to a plurality of first in-memory computing (IMC) macros, and performing a second convolution operation by allocating second chunks obtained by dividing a result of the first convolution operation to a plurality of second IMC macros.

公开(公告)号：US20240103809A1

公开(公告)日：2024-03-28

申请号：US18139567

申请日：2023-04-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dong-Jin CHANG ,  Soon-Wan KWON ,  Seok Ju YUN ,  Jaehyuk LEE ,  Sungmeen MYUNG ,  Daekun YOON

IPC: G06F7/507 ,  G06F7/504 ,  G06F7/544

CPC classification number: G06F7/507 ,  G06F7/504 ,  G06F7/5443

Abstract: Provided is a computation method of a memory processor configured to perform an operation between a first vector including first elements and a second vector including second elements, the first elements including respective first bits and the second elements including respective second bits, the method performed by the memory processor including: applying, to single-bit operation gates, the respective first bits and the respective second bits; obtaining bit operation result sum values for the respective first and second elements based on bit operation results obtained using the single-bit operation gates; and obtaining an operation result of the first vector and the second vector based on the bit operation result sum value.

公开(公告)号：US20220365752A1

公开(公告)日：2022-11-17

申请号：US17542833

申请日：2021-12-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyungwoo LEE ,  Seungchul JUNG ,  Sang Joon KIM ,  Sungmeen MYUNG

IPC: G06F7/544 ,  G06F7/523 ,  G06F7/50 ,  G11C11/40

Abstract: A multiply-accumulate (MAC) computation circuit includes: a source bit cell block configured to determine a MAC operation result of an input signal based on a plurality of source bit cells; a replica bit cell block comprising a plurality of replica bit cells corresponding to the plurality of source bit cells; and a readout circuit configured to read out a digital value of the MAC operation result using the replica bit cell block.