-
公开(公告)号：US20250094127A1
公开(公告)日：2025-03-20
申请号：US18969509
申请日：2024-12-05
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Seungchul JUNG , Sang Joon KIM , Sungmeen MYUNG , Seok Ju YUN , Seungkeun YOON
Abstract: A computing device for performing a digital pulse-based crossbar operation and a method of operating the computing device. The computing device includes a plurality of input lines to which a pulse is selectively input in a sequential manner based on a corresponding input signal; a plurality of output lines crossing the input lines; a plurality of elements, each element being disposed at a cross point between a corresponding input line and a corresponding output line to transfer, to the corresponding output line, a pulse input to the corresponding input line in response to a corresponding weight being a first value; and a plurality of pulse counters, each pulse counter counting a number of pulses output from a corresponding output line.
-
公开(公告)号：US20240112004A1
公开(公告)日：2024-04-04
申请号：US18115891
申请日：2023-03-01
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Jangho AN , Seungchul JUNG , Soon-Wan KWON
CPC classification number: G06N3/063 , G06F7/5443 , G06N3/04 , H10B10/12 , H10B10/18
Abstract: An apparatus including a memory layer including a plurality of front-end-of-line (FEOL) memory cells and a logic layer including plural arithmetic logic gates including back-end-of-line (BEOL) transistors, the plurality of BEOL transistors being vertically stacked on respective upper ends of the plurality of memory cells, wherein each of multiple transistors of the plurality of BEOL transistors operates as a multiplier and is configured to provide an operation result with respect to first values stored in corresponding memory cells of the plurality of memory cells.
-
公开(公告)号：US20240069867A1
公开(公告)日：2024-02-29
申请号：US18351039
申请日：2023-07-12
Applicant: Samsung Electronics Co., Ltd.
Inventor： Seok Ju YUN , Jaehyuk LEE , Seungchul JUNG , Soon-Wan KWON , Sungmeen MYUNG , Daekun YOON , Dong-Jin CHANG
CPC classification number: G06F7/523 , G06F7/501 , G06F7/5443 , G11C7/109
Abstract: An apparatus and method with in-memory computing (IMC) are provided. An in-memory computing (IMC) circuit includes a plurality of memory banks, each memory bank including a bit cell configured to store a weight value and an operator configured to receive an input value, the operator being connected to the bit cell such that the operator upon receiving the input value outputs a logic operation result between the input value and the weight value, and a logic gate configured to receive the logic operation result of each of the memory banks.
-
公开(公告)号：US20180062515A1
公开(公告)日：2018-03-01
申请号：US15599655
申请日：2017-05-19
Applicant: Samsung Electronics Co., Ltd.
Inventor： Seungchul JUNG
Abstract: A voltage converting apparatus includes a plurality of output channels configured to provide a plurality of output voltages, a main energy transfer circuit configured to transfer, through an inductor, energy of an input power supply to a target output channel among the output channels, and an auxiliary energy transfer circuit connected to one of the output channels.
-
公开(公告)号：US20170180988A1
公开(公告)日：2017-06-22
申请号：US15241903
申请日：2016-08-19
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Sang Joon KIM , Chang Soon PARK , Jong Wook LEE , Seungchul JUNG
CPC classification number: H04W12/06 , A61B5/04 , A61B5/1123 , A61B5/117 , A61B5/6887 , A61B2562/0219 , A61B2562/0247 , G06F3/03545 , G06K9/00006 , G06K9/00167 , G06K9/222 , H04L63/0861 , H04M1/7253
Abstract: A user authentication apparatus includes: a motion sensor configured to receive motion data associated with a motion of a body of the user authentication apparatus; a biometric sensor configured to receive biometric data associated with a user of the user authentication apparatus; and a processor configured to identify a signature of the user based on the motion data, and authenticate the user based on the identified signature and the biometric data.
-
Patent Agency Ranking
公开(公告)号：US20240177768A1
公开(公告)日：2024-05-30
申请号：US18350416
申请日：2023-07-11
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Seungchul JUNG , Seok Ju YUN , Soon-Wan KWON
IPC: G11C11/412 , H03K19/20 , H03K19/21
CPC classification number: G11C11/412 , H03K19/20 , H03K19/215
Abstract: An apparatus includes a static random access memory (SRAM) cell including a first inverter and a second inverter, and a third inverter including a first inverter transistor and a second inverter transistor. An output terminal of the first inverter is connected to a source terminal of the second inverter transistor.
-
公开(公告)号：US20230046817A1
公开(公告)日：2023-02-16
申请号：US17974852
申请日：2022-10-27
Applicant: Samsung Electronics Co., Ltd.
Inventor： Yongmin JU , Sangjoon KIM , Hyungwoo LEE , Seungchul JUNG
IPC: G11C11/54 , G11C11/4074 , G11C11/4076 , G11C11/4091
Abstract: An in-memory processing apparatus includes: a memory cell array comprising memory cell groups configured to generate current sums of column currents flowing through respective column lines in response to input signals input through row lines; voltage controlled delay circuits configured to output, in response to an input of a start signal at a first time point, stop signals at second time points delayed by delay times determined based on magnitudes of applied sampling voltages corresponding to the current sums; a time-digital converter configured to perform time-digital conversion at the second time points; and sampling resistors connected to the column lines, wherein the time-digital converter is configured to reset a counter at the first time point, and output counting values as digital values at the second time points.
-
公开(公告)号：US20220019885A1
公开(公告)日：2022-01-20
申请号：US17195917
申请日：2021-03-09
Applicant: Samsung Electronics Co., Ltd.
Inventor： Seungchul JUNG , Sangjoon KIM , Sungmeen MYUNG
Abstract: A processing device includes: a plurality of bitcells, each of the plurality of bitcells including: a variable resistor layer including a plurality of active variable resistors and a plurality of inactive variable resistors; an active layer including a plurality of switches configured to control either one of a voltage to be applied between ends of each of the active variable resistors and a current flowing to each of the active variable resistors; and a plurality of metal layers including wires electrically connecting the active variable resistors to the switches, wherein at least one of the plurality of bitcells includes a via penetrating through the variable resistor layer and connecting at least one of the switches to at least one of the active variable resistors.
-
公开(公告)号：US20200185955A1
公开(公告)日：2020-06-11
申请号：US16788493
申请日：2020-02-12
Applicant: Samsung Electronics Co., Ltd.
Inventor： Seungchul JUNG , JongPal KIM
Abstract: Provided are a voltage generating method and apparatus. A wireless power device includes a boosting circuit configured to generate a high voltage, and a switch arrangement circuit configured to selectively transmit energy to the boosting circuit, for the generating of the high voltage, using an inductor included in a resonator and in response to a build-up request for the high voltage.
-
公开(公告)号：US20200052529A1
公开(公告)日：2020-02-13
申请号：US16656944
申请日：2019-10-18
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Seungchul JUNG , Jongpal KIM , Wonseok LEE
Abstract: A resonator and resonator method are provided. The resonator includes an inductor, a capacitor, and a switch configured to maintain energy in at least one of the inductor and the capacitor for a select period of time and to enable variability of energy in the at least one of the inductor and the capacitor for another period of time, to set a resonating frequency of the inductor and the capacitor.
-
-
-
-
-
-
-
-
-
Search Results
36
records
(took 0.02 seconds)
