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公开(公告)号：US20220019884A1
公开(公告)日：2022-01-20
申请号：US17194571
申请日：2021-03-08
Applicant: Samsung Electronics Co., Ltd.
Inventor： Seungchul JUNG , Sangjoon KIM , Sungmeen MYUNG
IPC: G06N3/063 , G11C11/4094
Abstract: A processing device includes: a plurality of bitcells, each of the plurality of bitcells including: a variable resistor layer including a plurality of active variable resistors and a plurality of inactive variable resistors; an active layer including a plurality of switches configured to control either one of a voltage to be applied between ends of each of the active variable resistors and a current flowing to each of the active variable resistors; and a plurality of metal layers including wires electrically connecting the active variable resistors to the switches, wherein at least one of the plurality of bitcells includes a via penetrating through the variable resistor layer and connecting at least one of the switches to at least one of the active variable resistors.
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公开(公告)号：US20220004852A1
公开(公告)日：2022-01-06
申请号：US17150891
申请日：2021-01-15
Applicant: Samsung Electronics Co., Ltd.
Inventor： Yongmin JU , Sangjoon KIM , Hyungwoo LEE , Seungchul JUNG
IPC: G06N3/063 , G06N3/04 , G11C11/4076 , G11C11/4074
Abstract: An in-memory processing apparatus includes: a memory cell array comprising memory cell groups configured to generate current sums of column currents flowing through respective column lines in response to input signals input through row lines; voltage controlled delay circuits configured to output, in response to an input of a start signal at a first time point, stop signals at second time points delayed by delay times determined based on magnitudes of applied sampling voltages corresponding to the current sums; and a time-digital converter configured to perform time-digital conversion at the second time points.
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公开(公告)号：US20160191517A1
公开(公告)日：2016-06-30
申请号：US14983112
申请日：2015-12-29
Applicant: Samsung Electronics Co., Ltd.
Inventor： Chisung BAE , HaiBing REN , YongNan JI , Xuetao FENG , Biao WANG , Sangjoon KIM
IPC: H04L29/06
CPC classification number: H04L63/0861 , A61B5/0452 , A61B5/117 , A61B5/7246
Abstract: A method and apparatus for authenticating a user are provided. An authentication apparatus includes a data set generator configured to generate an authentication data set by extracting waveforms from a biosignal of a user, a similarity calculator configured to match each of the extracted waveforms to registered waveforms included in a registration data set, and calculate a similarity between each of the extracted waveforms and the registered waveforms, and an auxiliary similarity calculator configured to extract a representative authentication waveform indicating a representative waveform of the extracted waveforms and a representative registration waveform indicating a representative waveform of the registered waveforms, and calculate a similarity between the representative authentication waveform and the representative registration waveform.
Abstract translation: 提供了一种用于认证用户的方法和装置。 一种认证装置，包括数据组发生器，被配置为通过从用户的生物信号提取波形来生成认证数据集;相似度计算器，被配置为将每个提取的波形与注册数据集中包括的注册波形相匹配，并且计算相似度 以及辅助相似度计算器，被配置为提取表示提取的波形的代表性波形的代表性认证波形，以及表示所登记波形的代表性波形的代表登记波形，并且计算出所述波形的相似度 代表认证波形和代表性注册波形。
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公开(公告)号：US20230078279A1
公开(公告)日：2023-03-16
申请号：US17992143
申请日：2022-11-22
Applicant: Samsung Electronics Co., Ltd.
Inventor： Hyungwoo LEE , Sangjoon KIM , Yongmin JU
Abstract: An apparatus for performing in-memory processing includes a memory cell array of memory cells configured to output a current sum of a column current flowing in respective column lines of the memory cell array based on an input signal applied to row lines of the memory cells, a sampling circuit, comprising a capacitor connected to each of the column lines, configured to be charged by a sampling voltage of a corresponding current sum of the column lines, and a processing circuit configured to compare a reference voltage and a currently charged voltage in the capacitor in response to a trigger pulse generated at a timing corresponding to a quantization level, among quantization levels, time-sectioned based on a charge time of the capacitor, and determine the quantization level corresponding to the sampling voltage by performing time-digital conversion when the currently charged voltage reaches the reference voltage.
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公开(公告)号：US20220326910A1
公开(公告)日：2022-10-13
申请号：US17473139
申请日：2021-09-13
Applicant: Samsung Electronics Co., Ltd.
Inventor： Sungmeen MYUNG , Seungchul JUNG , Sangjoon KIM
Abstract: A multi-bit cell includes: a memory storing a weight resistance corresponding to a multi-bit weight; a current source configured to apply a current to the memory to generate a weight voltage from the weight resistance; a plurality of multiplexers connected to each other in parallel and connected to the memory in series, each of the multiplexers being configured to output one signal of the weight voltage and a first fixed voltage based on a multi-bit input; and a plurality of capacitors connected to the plurality of multiplexers, respectively, each of the capacitors being configured to store a respective weight capacitance, and to generate charge data by performing an operation on the outputted signal and the weight capacitance.
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Patent Agency Ranking
6.发明申请公开(公告)号：US20210390382A1
公开(公告)日：2021-12-16
申请号：US17084829
申请日：2020-10-30
Applicant: Samsung Electronics Co., Ltd.
Inventor： Soonwan KWON , Minjie KIM , Sangjoon KIM
Abstract: A neural network apparatus performs multiply-accumulate (MAC) operations with respect to fractions of weights and input activations in a block floating-point format by using an analog crossbar array, performs addition operations with respect to shared exponents of weights and input activations in a block floating-point format by using a digital computing circuit, and outputs a partial sum of floating-point output activations by combining the result of the MAC operations and the result of the addition operations.
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公开(公告)号：US20220193407A1
公开(公告)日：2022-06-23
申请号：US17551696
申请日：2021-12-15
Applicant: SAMSUNG ELECTRONICS CO., LTD. , NORTHEASTERN UNIVERSITY
Inventor： Junyeub SUH , Sangjoon KIM , Hui FANG , Jaehyeon RYU
Abstract: An implant system includes an electrode portion comprising plural electrodes to perform nerve stimulation and nerve sensing, an impedance controller configured to selectively connect the plural electrodes between a stimulator to perform nerve stimulation and a sensor to perform nerve sensing based on a control signal, and set an impedance of each of the plural electrodes, and a processor configured to control a contact impedance by the plural electrodes by generating the control signal to control at least one of plural switches connected respectively to the plural electrodes, or variable resistors connected respectively to the plural electrodes, based on at least one of a selectively set purpose of the plural electrodes or a position of an electrode to which nerve stimulation is to be provided.
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公开(公告)号：US20230046817A1
公开(公告)日：2023-02-16
申请号：US17974852
申请日：2022-10-27
Applicant: Samsung Electronics Co., Ltd.
Inventor： Yongmin JU , Sangjoon KIM , Hyungwoo LEE , Seungchul JUNG
IPC: G11C11/54 , G11C11/4074 , G11C11/4076 , G11C11/4091
Abstract: An in-memory processing apparatus includes: a memory cell array comprising memory cell groups configured to generate current sums of column currents flowing through respective column lines in response to input signals input through row lines; voltage controlled delay circuits configured to output, in response to an input of a start signal at a first time point, stop signals at second time points delayed by delay times determined based on magnitudes of applied sampling voltages corresponding to the current sums; a time-digital converter configured to perform time-digital conversion at the second time points; and sampling resistors connected to the column lines, wherein the time-digital converter is configured to reset a counter at the first time point, and output counting values as digital values at the second time points.
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公开(公告)号：US20220019885A1
公开(公告)日：2022-01-20
申请号：US17195917
申请日：2021-03-09
Applicant: Samsung Electronics Co., Ltd.
Inventor： Seungchul JUNG , Sangjoon KIM , Sungmeen MYUNG
Abstract: A processing device includes: a plurality of bitcells, each of the plurality of bitcells including: a variable resistor layer including a plurality of active variable resistors and a plurality of inactive variable resistors; an active layer including a plurality of switches configured to control either one of a voltage to be applied between ends of each of the active variable resistors and a current flowing to each of the active variable resistors; and a plurality of metal layers including wires electrically connecting the active variable resistors to the switches, wherein at least one of the plurality of bitcells includes a via penetrating through the variable resistor layer and connecting at least one of the switches to at least one of the active variable resistors.
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公开(公告)号：US20210366542A1
公开(公告)日：2021-11-25
申请号：US17141474
申请日：2021-01-05
Applicant: Samsung Electronics Co., Ltd.
Inventor： Hyungwoo LEE , Sangjoon KIM , Yongmin JU
IPC: G11C13/00
Abstract: An apparatus for performing in-memory processing includes a memory cell array of memory cells configured to output a current sum of a column current flowing in respective column lines of the memory cell array based on an input signal applied to row lines of the memory cells, a sampling circuit, comprising a capacitor connected to each of the column lines, configured to be charged by a sampling voltage of a corresponding current sum of the column lines, and a processing circuit configured to compare a reference voltage and a currently charged voltage in the capacitor in response to a trigger pulse generated at a timing corresponding to a quantization level, among quantization levels, time-sectioned based on a charge time of the capacitor, and determine the quantization level corresponding to the sampling voltage by performing time-digital conversion when the currently charged voltage reaches the reference voltage.
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