公开(公告)号：US20200295023A1

公开(公告)日：2020-09-17

申请号：US16886021

申请日：2020-05-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Young-Bae YOON ,  Joong-Shik SHIN ,  Kwang-Ho KIM ,  Hyun-Mog PARK

IPC: H01L27/11565 ,  H01L27/11582 ,  H01L27/11575 ,  H01L27/11568 ,  H01L27/11578

Abstract: A vertical memory device includes a channel, gate lines, and a cutting pattern, respectively, on a substrate. The channel extends in a first direction substantially perpendicular to an upper surface of the substrate. The gate lines are spaced apart from each other in the first direction. Each of the gate lines surrounds the channel and extends in a second direction substantially parallel to the upper surface of the substrate. The cutting pattern includes a first cutting portion extending in the first direction and cutting the gate lines, and a second cutting portion crossing the first cutting portion and merged with the first cutting portion.

公开(公告)号：US20200075101A1

公开(公告)日：2020-03-05

申请号：US16659715

申请日：2019-10-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Da Woon JEONG ,  Sung-Hun LEE ,  Seokjung YUN ,  Hyunmog PARK ,  JoongShik SHIN ,  Young-Bae YOON

IPC: G11C16/04 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11582 ,  H01L21/768 ,  G11C5/02 ,  G11C5/06 ,  H01L49/02

Abstract: Three-dimensional (3D) semiconductor memory devices and methods of manufacturing the same are provided. Three-dimensional (3D) semiconductor memory devices may include a substrate including a cell array region and a connection region, a lower stack structure including a plurality of lower electrodes vertically stacked on the substrate, the lower stack structure having a first stair step structure extending in a first direction on the connection region and a second stair step structure extending in a second direction substantially perpendicular to the first direction on the connection region, and a plurality of intermediate stack structures vertically stacked on the lower stack structure. Each of the intermediate stack structures includes a plurality of intermediate electrodes vertically stacked and has a third stair step structure extending in the second direction on the connection region. Each of the intermediate stack structures exposes the third stair step structure of the intermediate stack structure disposed thereunder.