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    SEMICONDUCTOR DEVICE AND ELECTRONIC SYSTEM INCLUDING THE SAME
    1.
    发明公开
    SEMICONDUCTOR DEVICE AND ELECTRONIC SYSTEM INCLUDING THE SAME 审中-公开

    公开(公告)号：US20230329012A1

    公开(公告)日：2023-10-12

    申请号：US18149929

    申请日：2023-01-04

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Bongyong LEE ,  Taeyoung KIM ,  Hyunmog PARK ,  Siyeon CHO

    IPC: H10B80/00 ,  H10B41/27 ,  H10B43/27

    CPC classification number: H10B80/00 ,  H10B43/27 ,  H10B41/27

    Abstract: A semiconductor device may include a first substrate structure including a substrate, circuit elements on the substrate, and first bonding layers on the circuit elements, and a second substrate structure on the first substrate structure. The second substrate structure may include a plate layer, an intermediate insulating layer below the plate layer and including silicon nitride, gate electrodes below the intermediate insulating layer and stacked to be spaced apart from each other in a vertical direction, a channel structure in a channel hole passing through the intermediate insulating layer and the gate electrodes and including a semiconductor layer, and second bonding layers connected to the first bonding layers. The channel hole may have a first width in a first portion passing through the gate electrodes and a second width, wider than the first width, in a second portion passing through the intermediate insulating layer.

    THREE-DIMENSIONAL NON-VOLATILE MEMORY DEVICE INCLUDING HORIZONTAL CHANNEL REGION
    3.
    发明公开
    THREE-DIMENSIONAL NON-VOLATILE MEMORY DEVICE INCLUDING HORIZONTAL CHANNEL REGION 审中-公开

    公开(公告)号：US20230292522A1

    公开(公告)日：2023-09-14

    申请号：US18055974

    申请日：2022-11-16

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Daewon HA ,  Kyunghwan LEE ,  Hyunmog PARK

    IPC: H01L21/02

    CPC classification number: H10B51/20 ,  H10B51/10 ,  H10B51/40

    Abstract: A three-dimensional non-volatile memory device includes a memory cell array including a plurality of memory cells repeatedly arranged in a first lateral direction, a second lateral direction, and a vertical direction on a substrate. The first lateral direction and the second lateral direction are parallel to a main surface of the substrate and perpendicular to each other, and the vertical direction is perpendicular to the main surface of the substrate. The memory cell array includes a plurality of horizontal channel regions and a vertical word line. The plurality of horizontal channel regions extend in the first lateral direction on the substrate. The plurality of horizontal channel regions overlap each other and are apart from each other in the vertical direction. The vertical word line passes through the plurality of horizontal channel regions in the vertical direction.

    MEMORY DEVICE
    5.
    发明申请
    MEMORY DEVICE 有权

    公开(公告)号：US20230021071A1

    公开(公告)日：2023-01-19

    申请号：US17949305

    申请日：2022-09-21

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Minhee CHO ,  Woobin SONG ,  Hyunmog PARK ,  Sangkil LEE

    IPC: G11C11/00 ,  H01L27/108 ,  H01L27/1159 ,  G11C11/4096 ,  G11C11/22 ,  H01L27/11592

    Abstract: A memory device includes a substrate including first and second regions, the first region having first wordlines and first bitlines, and the second region having second wordlines and second bitlines, a first memory cell array including first memory cells in the first region, the first memory cell array having volatility, and each of the first memory cells including a cell switch having a first channel region adjacent to a corresponding first wordline of the first wordlines, and a capacitor connected to the cell switch, and a second memory cell array including second memory cells in the second region, the second memory cell array having non-volatility, and each of the second memory cells including a second channel region adjacent to a corresponding second wordline of the second wordlines, and a ferroelectric layer between the corresponding second wordline of the second wordlines and the second channel region.

    RESISTIVE MEMORY DEVICE
    6.
    发明申请
    RESISTIVE MEMORY DEVICE 有权

    公开(公告)号：US20220310698A1

    公开(公告)日：2022-09-29

    申请号：US17526262

    申请日：2021-11-15

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Hyunmog PARK ,  Jungyu LEE ,  Daehwan KANG ,  Sungho EUN

    IPC: H01L27/24

    Abstract: A resistive memory device includes: memory cells overlapping one another in a vertical direction within a cell array region and each including a switching element and a variable resistive element; first conductive lines each being connected to the switching element; a second conductive line connected to the variable resistive element and conductive pads arranged in a connection region and connected to respective one ends of the first conductive lines, respectively, and having different lengths in the second horizontal direction. A lower conductive pad from among the conductive pads includes a first portion covered by an upper conductive pad, and a second portion not covered by the upper conductive pad, and a thickness of each of the first and second portions in the vertical direction is greater than a thickness of each of the first conductive lines in the vertical direction.

    SEMICONDUCTOR DEVICES AND DATA STORAGE SYSTEMS INCLUDING THE SAME
    7.
    发明公开
    SEMICONDUCTOR DEVICES AND DATA STORAGE SYSTEMS INCLUDING THE SAME 审中-公开

    公开(公告)号：US20230337438A1

    公开(公告)日：2023-10-19

    申请号：US18152310

    申请日：2023-01-10

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Hyunmog PARK ,  Bongyong LEE

    IPC: H10B51/30 ,  H10B51/20 ,  H10B80/00

    CPC classification number: H10B51/30 ,  H10B51/20 ,  H10B80/00

    Abstract: A semiconductor device includes gate electrodes extending in a first direction, first and second vertical structures passing through the gate electrodes, a first upper interconnection, and a second upper interconnection structure, the first and second vertical structures including a back gate electrode, a ferroelectric material layer, a channel layer, and a gate insulating layer, the first upper interconnection structure including bit lines extending in a second direction, a first contact plug connected to a lower surface of a first back gate electrode of the first vertical structure, and a first back gate interconnection extending between the bit lines in the second direction and connected to the first contact plug, and the second upper interconnection structure including a second contact plug connected to an upper surface of a second back gate electrode of the second vertical structure, and a second back gate interconnection extending in the second direction and connected to the second contact plug.

    MEMORY DEVICE
    8.
    发明申请
    MEMORY DEVICE 有权

    公开(公告)号：US20210280230A1

    公开(公告)日：2021-09-09

    申请号：US17330828

    申请日：2021-05-26

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Minhee CHO ,  Woobin SONG ,  Hyunmog PARK ,  Sangkil LEE

    IPC: G11C11/00 ,  H01L27/1159 ,  H01L27/108 ,  G11C11/4096 ,  G11C11/22 ,  H01L27/11592

    Abstract: A memory device includes a substrate including first and second regions, the first region having first wordlines and first bitlines, and the second region having second wordlines and second bitlines, a first memory cell array including first memory cells in the first region, the first memory cell array having volatility, and each of the first memory cells including a cell switch having a first channel region adjacent to a corresponding first wordline of the first wordlines, and a capacitor connected to the cell switch, and a second memory cell array including second memory cells in the second region, the second memory cell array having non-volatility, and each of the second memory cells including a second channel region adjacent to a corresponding second wordline of the second wordlines, and a ferroelectric layer between the corresponding second wordline of the second wordlines and the second channel region.

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