公开(公告)号：US10957795B2

公开(公告)日：2021-03-23

申请号：US16845591

申请日：2020-04-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yong Hee Park ,  Myung Gil Kang ,  Young-Seok Song ,  Keon Yong Cheon

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/08 ,  H01L29/06 ,  H01L29/66 ,  H01L27/12

Abstract: A vertical field effect transistor (VFET) including a first source/drain region, a channel structure upwardly protruding from the first source/drain region and configured to serve as a channel, the channel structure having a two-dimensional structure in a plan view, the channel structure having an opening at at least one side thereof, the channel structure including one or two first portions and one or more second portions, the one or two first portion extending in a first direction, and the one or more second portions connected to corresponding one or more of the one or more first portions and extending in a second direction, the second direction being different from the first direction, a gate structure horizontally surrounding the channel structure, and a second source/drain region upwardly on the channel structure may be provided.

公开(公告)号：US20180033890A1

公开(公告)日：2018-02-01

申请号：US15728965

申请日：2017-10-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yong-hee Park ,  Young-Seok Song ,  Ji-Soo Chang ,  Young-Chul Hwang

IPC: H01L29/78 ,  H01L27/088 ,  H01L29/66 ,  H01L27/092 ,  H01L21/8234

CPC classification number: H01L29/7856 ,  H01L21/823431 ,  H01L21/823437 ,  H01L27/0886 ,  H01L27/0924 ,  H01L29/66545

Abstract: An IC device includes a substrate including a device region having a fin-type active region and a deep trench region; a gate line that extends in a direction intersecting the fin-type active region; and an inter-device isolation layer that fills the deep trench region. The gate line includes a first gate portion that extends on the device region to cover the fin-type active region and has a flat upper surface at a first level and a second gate portion that extends on the deep trench region to cover the inter-device isolation layer while being integrally connected to the first gate portion and has an upper surface at a second level that is closer to the substrate than the first level.