Vertical field-effect transistor (VFET) devices and methods of forming the same

    公开(公告)号:US11521902B2

    公开(公告)日:2022-12-06

    申请号:US17032085

    申请日:2020-09-25

    Abstract: Vertical field-effect transistor (VFET) devices and methods of forming the devices are provided. The methods may include forming a channel region including a first channel region and a second channel region, forming a first cavity in the substrate, forming a first bottom source/drain in the first cavity, forming a second cavity in the substrate, and forming a second bottom source/drain in the second cavity. The first cavity may expose a lower surface of the first channel region, and the second cavity may expose a lower surface of the second channel region. The method may also include after forming the first bottom source/drain and the second bottom source/drain, removing a portion of the channel region between the first channel region and the second channel region to separate the first channel region from the second channel region.

    VERTICAL FIELD-EFFECT TRANSISTOR (VFET) DEVICES AND METHODS OF FORMING THE SAME

    公开(公告)号:US20200020599A1

    公开(公告)日:2020-01-16

    申请号:US16434211

    申请日:2019-06-07

    Abstract: Vertical field-effect transistor (VFET) devices and methods of forming the devices are provided. The methods may include forming a channel region including a first channel region and a second channel region, forming a first cavity in the substrate, forming a first bottom source/drain in the first cavity, forming a second cavity in the substrate, and forming a second bottom source/drain in the second cavity. The first cavity may expose a lower surface of the first channel region, and the second cavity may expose a lower surface of the second channel region. The method may also include after forming the first bottom source/drain and the second bottom source/drain, removing a portion of the channel region between the first channel region and the second channel region to separate the first channel region from the second channel region.

    Vertical field-effect transistor (VFET) devices and methods of forming the same

    公开(公告)号:US10818560B2

    公开(公告)日:2020-10-27

    申请号:US16434211

    申请日:2019-06-07

    Abstract: Vertical field-effect transistor (VFET) devices and methods of forming the devices are provided. The methods may include forming a channel region including a first channel region and a second channel region, forming a first cavity in the substrate, forming a first bottom source/drain in the first cavity, forming a second cavity in the substrate, and forming a second bottom source/drain in the second cavity. The first cavity may expose a lower surface of the first channel region, and the second cavity may expose a lower surface of the second channel region. The method may also include after forming the first bottom source/drain and the second bottom source/drain, removing a portion of the channel region between the first channel region and the second channel region to separate the first channel region from the second channel region.

    Vertical tunneling field effect transistor and method for manufacturing the same

    公开(公告)号:US10164057B1

    公开(公告)日:2018-12-25

    申请号:US15878711

    申请日:2018-01-24

    Abstract: A vertical tunnel field effect transistor (VTFET) including a fin structure protruding from a substrate including a source/drain region, an epitaxially-grown source/drain structure on the fin structure, a cap including pillar portions, the pillar portions covering side surfaces of the epitaxially-grown source/drain structure and partially covering side surfaces of a top portion of the fin structure, a gate insulator covering remaining portions of the side surfaces of the fin structure under the pillar portions of the cap, a work function metal gate on the gate insulator, and a separation pattern surrounding a bottom portion of a fin structure such that the work function metal gate is vertically between the cap and the separation pattern, the separation pattern electrically isolating the work function metal gate from the source/drain region, and a method of manufacturing the same may be provided.

    Vertical field effect transistor having two-dimensional channel structure

    公开(公告)号:US10957795B2

    公开(公告)日:2021-03-23

    申请号:US16845591

    申请日:2020-04-10

    Abstract: A vertical field effect transistor (VFET) including a first source/drain region, a channel structure upwardly protruding from the first source/drain region and configured to serve as a channel, the channel structure having a two-dimensional structure in a plan view, the channel structure having an opening at at least one side thereof, the channel structure including one or two first portions and one or more second portions, the one or two first portion extending in a first direction, and the one or more second portions connected to corresponding one or more of the one or more first portions and extending in a second direction, the second direction being different from the first direction, a gate structure horizontally surrounding the channel structure, and a second source/drain region upwardly on the channel structure may be provided.

    Vertical tunneling field effect transistor and method for manufacturing the same

    公开(公告)号:US10892347B2

    公开(公告)日:2021-01-12

    申请号:US16197752

    申请日:2018-11-21

    Abstract: A vertical tunnel field effect transistor (VTFET) including a fin structure protruding from a substrate including a source/drain region, an epitaxially-grown source/drain structure on the fin structure, a cap including pillar portions, the pillar portions covering side surfaces of the epitaxially-grown source/drain structure and partially covering side surfaces of a top portion of the fin structure, a gate insulator covering remaining portions of the side surfaces of the fin structure under the pillar portions of the cap, a work function metal gate on the gate insulator, and a separation pattern surrounding a bottom portion of a fin structure such that the work function metal gate is vertically between the cap and the separation pattern, the separation pattern electrically isolating the work function metal gate from the source/drain region, and a method of manufacturing the same may be provided.

    Semiconductor device and method for fabricating the same

    公开(公告)号:US09966446B2

    公开(公告)日:2018-05-08

    申请号:US15353163

    申请日:2016-11-16

    Abstract: There is provided a semiconductor device to enhance operating characteristics by reducing parasitic capacitance between a gate electrode and other nodes. The semiconductor device includes: a substrate including an active region, and a field region directly adjacent to the active region; a first fin-type pattern protruding from the substrate in the active region; a first gate electrode disposed on the substrate, intersecting with the first fin-type pattern and including a first portion and a second portion, the first portion intersecting with the first fin-type pattern; a second gate electrode disposed on the substrate, intersecting with the first fin-type pattern and including a third portion and a fourth portion, the fourth portion facing the second portion, and the third portion intersecting with the first fin-type pattern and facing the first portion; a first interlayer insulating structure disposed between the first portion and the third portion, being on the substrate, and having a first dielectric constant; and a second interlayer insulating structure disposed between the second portion and the fourth portion, being on the substrate, and having a second dielectric constant which is different from the first dielectric constant.

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