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    ELECTRONIC APPARATUS AND METHOD FOR CONTROLLING ELECTRONIC APPARATUS THEREOF
    2.
    发明申请
    ELECTRONIC APPARATUS AND METHOD FOR CONTROLLING ELECTRONIC APPARATUS THEREOF 审中-公开

    公开(公告)号：US20200213515A1

    公开(公告)日：2020-07-02

    申请号：US16813080

    申请日：2020-03-09

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Jae-il JUNG ,  Jin-hyoung AN ,  Min-chul KIM ,  Young-kuk KIM ,  Yong-jin KIM ,  Sung-rae CHO

    IPC: H04N5/232

    Abstract: An electronic apparatus for acquiring a panorama image using a plurality of cameras and a method for controlling the electronic apparatus thereof are provided. The electronic apparatus includes a plurality of cameras for capturing an image, a sensor for acquiring movement information, and a processor for determining individual movement information of the plurality of cameras with reference to a predefined location using movement information acquired through the sensor, acquiring a plurality of images through the plurality of cameras based on the individual movement information and generating a panorama image using the plurality of photographed images.

    SEMICONDUCTOR DEVICE AND METHOD OF FORMING THEREOF
    3.
    发明申请
    SEMICONDUCTOR DEVICE AND METHOD OF FORMING THEREOF 审中-公开
    半导体器件及其形成方法

    公开(公告)号：US20150311297A1

    公开(公告)日：2015-10-29

    申请号：US14556870

    申请日：2014-12-01

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Badro IM ,  Ki-Vin IM ,  Young-kuk KIM ,  Han-jin LIM ,  In-Seak HWANG

    IPC: H01L29/423 ,  H01L29/06 ,  H01L29/10

    CPC classification number: H01L29/4236 ,  H01L21/76224 ,  H01L27/10876 ,  H01L27/10894 ,  H01L29/78

    Abstract: Provided are a semiconductor device and a method of forming thereof. The semiconductor device includes a substrate having an isolating trench defining active areas, gate structures formed in the active area and crossing the isolating trench, a first protection layer formed on the active area of the substrate, and a second protection layer formed on the first protection layer, wherein, in a first isolating area in which the gate structure and the isolating trench cross, the first protection layer is conformally formed on an inner wall and bottom of the isolating trench, and the second protection layer is formed on the first protection layer formed on the bottom of the isolating trench.

    Abstract translation: 提供一种半导体器件及其形成方法。 半导体器件包括具有限定有源区的隔离沟槽的衬底，形成在有源区中并与隔离沟交叉的栅极结构，形成在衬底的有源区上的第一保护层和形成在第一保护层上的第二保护层 其中，在所述栅极结构和所述隔离沟槽交叉的第一隔离区域中，所述第一保护层保形地形成在所述隔离沟槽的内壁和底部上，并且所述第二保护层形成在所述第一保护层上 形成在隔离沟槽的底部。

    SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
    5.
    发明申请
    SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 审中-公开
    半导体器件及其制造方法

    公开(公告)号：US20160118331A1

    公开(公告)日：2016-04-28

    申请号：US14695281

    申请日：2015-04-24

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Young-kuk KIM ,  Chan-mi LEE ,  Sang-kwan KIM ,  Young-wook PARK

    IPC: H01L23/528 ,  H01L27/088

    CPC classification number: H01L27/10894 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A semiconductor device includes a substrate including a cell array region having a first active region and a peripheral circuit region having a second active region, an insulating layer pattern on the substrate and including a hole corresponding with the first active region, a DC conductive pattern in the hole, connected to the first active region, and buried in the substrate, a bit line connected to the DC conductive pattern and including a first bit line conductive pattern contacting the DC conductive pattern and covering a top surface of the insulating layer pattern, and a gate insulating layer and a gate electrode structure on the second active region, the gate electrode structure including a gate conductive pattern and a first gate electrode conductive pattern, the first gate electrode conductive pattern including a same material as the first bit line conductive pattern.

    Abstract translation: 一种半导体器件包括：衬底，包括具有第一有源区的单元阵列区和具有第二有源区的外围电路区，衬底上的绝缘层图案，并且包括与第一有源区对应的空穴; DC导电图案， 所述孔连接到所述第一有源区并且埋入所述衬底中，位线连接到所述DC导电图案，并且包括接触所述DC导电图案并覆盖所述绝缘层图案的顶表面的第一位线导电图案，以及 栅极绝缘层和栅极电极结构，所述栅电极结构包括栅极导电图案和第一栅电极导电图案，所述第一栅电极导电图案包括与所述第一位线导电图案相同的材料。

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