公开(公告)号：US20170316950A1

公开(公告)日：2017-11-02

申请号：US15444381

申请日：2017-02-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyungmun BYUN ,  Sinhae DO ,  Badro IM

IPC: H01L21/308 ,  H01L21/3213 ,  H01L21/28

CPC classification number: H01L21/3086 ,  H01L21/0337 ,  H01L21/28017 ,  H01L21/32139

Abstract: A method for forming patterns of a semiconductor device includes sequentially forming a hard mask layer, a sacrificial layer, and an anti-reflection layer on a substrate, the substrate including a cell region and a peripheral circuit region, patterning the sacrificial layer to form a first sacrificial pattern on the cell region and a second sacrificial pattern on the peripheral circuit region, forming spacers covering sidewalls of the first and second sacrificial patterns, and removing the first sacrificial pattern. The anti-reflection layer includes a lower anti-reflection layer and an upper anti-reflection layer which are formed of materials different from each other. In the patterning of the sacrificial layer, the anti-reflection layer is patterned to form a first anti-reflection pattern on the first sacrificial pattern and a second anti-reflection pattern on the second sacrificial pattern. The second anti-reflection pattern remains when the first sacrificial pattern is removed.

公开(公告)号：US20150311297A1

公开(公告)日：2015-10-29

申请号：US14556870

申请日：2014-12-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Badro IM ,  Ki-Vin IM ,  Young-kuk KIM ,  Han-jin LIM ,  In-Seak HWANG

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/10

CPC classification number: H01L29/4236 ,  H01L21/76224 ,  H01L27/10876 ,  H01L27/10894 ,  H01L29/78

Abstract: Provided are a semiconductor device and a method of forming thereof. The semiconductor device includes a substrate having an isolating trench defining active areas, gate structures formed in the active area and crossing the isolating trench, a first protection layer formed on the active area of the substrate, and a second protection layer formed on the first protection layer, wherein, in a first isolating area in which the gate structure and the isolating trench cross, the first protection layer is conformally formed on an inner wall and bottom of the isolating trench, and the second protection layer is formed on the first protection layer formed on the bottom of the isolating trench.

Abstract translation: 提供一种半导体器件及其形成方法。 半导体器件包括具有限定有源区的隔离沟槽的衬底，形成在有源区中并与隔离沟交叉的栅极结构，形成在衬底的有源区上的第一保护层和形成在第一保护层上的第二保护层 其中，在所述栅极结构和所述隔离沟槽交叉的第一隔离区域中，所述第一保护层保形地形成在所述隔离沟槽的内壁和底部上，并且所述第二保护层形成在所述第一保护层上 形成在隔离沟槽的底部。

公开(公告)号：US20180102260A1

公开(公告)日：2018-04-12

申请号：US15700491

申请日：2017-09-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sun-Hye HWANG ,  Youn-Joung CHO ,  Won-Woong CHUNG ,  Nam-Gun KIM ,  Kong-Soo LEE ,  Badro IM ,  Yoon-Chul CHO

IPC: H01L21/3213 ,  H01L21/311

CPC classification number: H01L21/32139 ,  C23C16/0272 ,  C23C16/04 ,  C23C16/24 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/3086 ,  H01L21/31144 ,  H01L21/32055 ,  H01L27/10885

Abstract: A method of forming a pattern includes forming an etch target layer on a substrate, forming sacrificial patterns on the etch target layer, the sacrificial patterns including a carbon-containing material, providing a silicon-sulfur compound or a sulfur-containing gas onto the sacrificial patterns to form a seed layer, providing a silicon precursor onto the seed layer to form silicon-containing mask patterns, and at least partially etching the etch target layer using the mask patterns.

公开(公告)号：US20180012775A1

公开(公告)日：2018-01-11

申请号：US15613822

申请日：2017-06-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyung-Mun BYUN ,  Badro IM ,  Hong-Rae KIM ,  Sin-Hae DO ,  Gyeong-Deok PARK

IPC: H01L21/48 ,  H01L21/764 ,  H01L21/308 ,  H01L21/28 ,  H01L21/285 ,  H01L21/8234 ,  H01L21/67

CPC classification number: H01L21/4885 ,  H01L21/28132 ,  H01L21/28194 ,  H01L21/28556 ,  H01L21/308 ,  H01L21/67138 ,  H01L21/764 ,  H01L21/768 ,  H01L21/823475

Abstract: In a method of manufacturing a semiconductor memory device, a plurality of first conductive structures including a first conductive pattern and a hard mask are sequentially stacked on a substrate. A plurality of preliminary spacer structures including first spacers, sacrificial spacers and second spacers are sequentially stacked on sidewalls of the conductive structures. A plurality of pad structures are formed on the substrate between the preliminary spacer structures, and define openings exposing an upper portion of the sacrificial spacers. A first mask pattern is formed to cover surfaces of the pad structures, and expose the upper portion of the sacrificial spacers. The sacrificial spacers are removed to form first spacer structures having respective air spacers, and the first spacer structures include the first spacers, the air spacers and the second spacers sequentially stacked on the sidewalls of the conductive structures.

公开(公告)号：US20140264517A1

公开(公告)日：2014-09-18

申请号：US14175076

申请日：2014-02-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Youngkuk KIM ,  Ho-Kyun AN ,  Jaehyun YEO ,  Badro IM ,  HanJin LIM ,  Sungho JANG ,  Insang JEON

IPC: H01L27/108 ,  H01L27/105

CPC classification number: H01L27/10894 ,  H01L21/823412 ,  H01L21/823462 ,  H01L27/10814 ,  H01L27/10861

Abstract: Semiconductor devices having a silicon-germanium channel layer and methods of forming the semiconductor devices are provided. The methods may include forming a silicon-germanium channel layer on a substrate in a peripheral circuit region and sequentially forming a first insulating layer and a second insulating layer on the silicon-germanium channel layer. The methods may also include forming a conductive layer on the substrate, which includes a cell array region and the peripheral circuit region, and patterning the conductive layer to form a conductive line in the cell array region and a gate electrode in the peripheral circuit region. The first insulating layer may be formed at a first temperature and the second insulating layer may be formed at a second temperature higher than the first temperature.

Abstract translation: 提供具有硅 - 锗沟道层的半导体器件和形成半导体器件的方法。 所述方法可以包括在外围电路区域中的衬底上形成硅 - 锗沟道层，并且在硅 - 锗沟道层上依次形成第一绝缘层和第二绝缘层。 该方法还可以包括在衬底上形成导电层，该导电层包括电池阵列区域和外围电路区域，以及图案化导电层以在电池阵列区域中形成导线以及在外围电路区域中形成栅极电极。 第一绝缘层可以在第一温度下形成，并且第二绝缘层可以在高于第一温度的第二温度下形成。