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1.发明授权公开(公告)号：US12185543B2
公开(公告)日：2024-12-31
申请号：US17742043
申请日：2022-05-11
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Sanghun Chun , Kwangyoung Jung , Youngji Noh , Junghwan Park , Jeehoon Han
Abstract: A semiconductor device includes a substrate, gate electrodes stacked and spaced apart from each other in a first direction perpendicular to an upper surface of the substrate, channel structures penetrating the gate electrodes, extending in the first direction, and each including a channel layer, separation regions penetrating the gate electrodes, extending in the first direction and a second direction perpendicular to the first direction, and spaced apart from each other in a third direction perpendicular to the first direction and the second direction, and crack prevention layers disposed on at least a portion of the separation regions, wherein each of the separation regions includes a lower region and upper regions spaced apart from each other in the second direction on the lower region and protruding upwardly from the lower region, and wherein the crack prevention layers are in contact with upper surfaces of the upper regions.
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Patent Agency Ranking
公开(公告)号：US12302563B2
公开(公告)日：2025-05-13
申请号：US17537744
申请日：2021-11-30
Applicant: Samsung Electronics Co., Ltd.
Inventor： Donghwan Kim , Shinhwan Kang , Youngji Noh , Jung-Hwan Park , Sanghun Chun
Abstract: Disclosed are three-dimensional semiconductor memory devices, electronic systems including the same, and methods of fabricating the same. The three-dimensional semiconductor memory device includes a substrate including a cell array region and an extension region, a peripheral circuit structure including peripheral transistors on the substrate, a stack structure including interlayer dielectric layers and gate electrodes that are alternately stacked on the peripheral circuit structure, contacts that penetrate the stack structure on the extension region and are electrically connected with the peripheral transistors and include a protruding part contacting a sidewall of one of the gate electrodes and a vertical part penetrating the stack structure, and dielectric patterns between the vertical part and respective sidewalls of the gate electrodes. Top and bottom surfaces of each of the dielectric patterns are respectively in contact with adjacent ones of the interlayer dielectric layers.
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公开(公告)号：US20240032303A1
公开(公告)日：2024-01-25
申请号：US18301597
申请日：2023-04-17
Applicant: Samsung Electronics Co., Ltd.
Inventor： Jongho WOO , Youngji Noh , Minjun Lee
Abstract: A three-dimensional semiconductor device includes a plate common source line, first and second word lines spaced apart from each other to at least partially define a vertical space therebetween, a channel pattern in the vertical space, a ferroelectric layer including a first portion between the channel pattern and the first word line, a second portion between the channel pattern and the second word line, and a third portion contacting the plate common source line, a bit line in the vertical space to contact the channel pattern and having a first width in a first horizontal direction, and a source line spaced apart from the bit line in the vertical space to contact the channel pattern, having a second width greater than the first width in the first horizontal direction, and having a source line contact portion inside the plate common source line.
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公开(公告)号：US20240172457A1
公开(公告)日：2024-05-23
申请号：US18497027
申请日：2023-10-30
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Youngji Noh , Jongho Woo , Jooheon Kang , Kyunghoon Kim , Myunghun Woo
IPC: H10B63/00
CPC classification number: H10B63/845 , H10B63/34
Abstract: A vertical memory device may include a cell stacked structure on a substrate, wherein the cell stacked structure includes an insulation layer pattern and a gate pattern are alternately and repeatedly stacked, and wherein the cell stacked structure extends in a first direction parallel to an upper surface of the substrate, and wherein an edge portion in the first direction of the cell stacked region is disposed in the second region and has a step portion having a step shape; an etch stop structure on an upper surface of each of gate patterns of the step portion of the cell stacked structure, wherein the etch stop structure includes a transition metal oxide; an insulating interlayer covering the cell stacked structure; and a contact plug passing through the insulating interlayer and the etch stop structure, wherein the contact plug contacts the upper surface of each of the gate patterns.
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公开(公告)号：US20220359563A1
公开(公告)日：2022-11-10
申请号：US17651633
申请日：2022-02-18
Applicant: Samsung Electronics Co., Ltd.
Inventor： Youngji Noh , Jung-Hwan Park , Kwangyoung Jung , Hyojoon Ryu , Jeehoon Han
IPC: H01L27/11582 , H01L27/11556 , H01L27/11519 , H01L27/11524 , H01L27/11526 , H01L27/11565 , H01L27/1157 , H01L27/11573 , H01L23/528
Abstract: Provided are three-dimensional semiconductor memory devices and electronic systems including the same. The device includes a substrate, stack structures each including interlayer dielectric layers and gate electrodes, which are alternately and repeatedly stacked on the substrate, vertical channel structures which penetrate the stack structures, and a separation structure, which extends in a first direction across between the stack structures. The separation structure includes first parts each having a pillar shape, which extend in a third direction perpendicular to a top surface of the substrate, and second parts, which extend between the interlayer dielectric layers from sidewalls of the first parts and which connect the first parts to each other in the first direction. The separation structure is spaced apart from the vertical channel structures in a second direction which intersects the first direction.
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公开(公告)号：US20220216151A1
公开(公告)日：2022-07-07
申请号：US17537744
申请日：2021-11-30
Applicant: Samsung Electronics Co., Ltd.
Inventor： Donghwan Kim , Shinhwan Kang , Youngji Noh , Jung-Hwan Park , Sanghun Chun
IPC: H01L23/535 , H01L23/522 , H01L27/11582 , H01L27/11573
Abstract: Disclosed are three-dimensional semiconductor memory devices, electronic systems including the same, and methods of fabricating the same. The three-dimensional semiconductor memory device includes a substrate including a cell array region and an extension region, a peripheral circuit structure including peripheral transistors on the substrate, a stack structure including interlayer dielectric layers and gate electrodes that are alternately stacked on the peripheral circuit structure, contacts that penetrate the stack structure on the extension region and are electrically connected with the peripheral transistors and include a protruding part contacting a sidewall of one of the gate electrodes and a vertical part penetrating the stack structure, and dielectric patterns between the vertical part and respective sidewalls of the gate electrodes. Top and bottom surfaces of each of the dielectric patterns are respectively in contact with adjacent ones of the interlayer dielectric layers.
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