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公开(公告)号：US09443734B2
公开(公告)日：2016-09-13
申请号：US14574907
申请日：2014-12-18
Applicant: Samsung Electronics Co., Ltd.
Inventor： Ki-Seok Lee , Jung-Hwan Park , Hyo-Jin Park , Kyu-Hyun Lee
IPC: H01L21/28 , H01L29/423 , H01L27/108
CPC classification number: H01L21/28008 , H01L27/10888 , H01L27/10891 , H01L27/10894 , H01L29/4236
Abstract: A semiconductor memory device and a manufacturing method of the semiconductor memory device are provided. The semiconductor memory device can include a substrate in which a cell area and a peripheral area are defined, a first gate insulating layer on the peripheral area, and a poly gate layer on the first gate insulating layer to form a combined stack, wherein the combined stack of the first gate insulating layer and the first poly gate layer is absent from the cell area.
Abstract translation: 提供半导体存储器件和半导体存储器件的制造方法。 半导体存储器件可以包括其中限定了单元区域和外围区域的基板，外围区域上的第一栅极绝缘层，以及在第一栅极绝缘层上形成组合堆叠的多晶硅栅极层，其中组合 第一栅极绝缘层和第一多晶硅层的堆叠不存在于电池区域中。
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公开(公告)号：US12302563B2
公开(公告)日：2025-05-13
申请号：US17537744
申请日：2021-11-30
Applicant: Samsung Electronics Co., Ltd.
Inventor： Donghwan Kim , Shinhwan Kang , Youngji Noh , Jung-Hwan Park , Sanghun Chun
Abstract: Disclosed are three-dimensional semiconductor memory devices, electronic systems including the same, and methods of fabricating the same. The three-dimensional semiconductor memory device includes a substrate including a cell array region and an extension region, a peripheral circuit structure including peripheral transistors on the substrate, a stack structure including interlayer dielectric layers and gate electrodes that are alternately stacked on the peripheral circuit structure, contacts that penetrate the stack structure on the extension region and are electrically connected with the peripheral transistors and include a protruding part contacting a sidewall of one of the gate electrodes and a vertical part penetrating the stack structure, and dielectric patterns between the vertical part and respective sidewalls of the gate electrodes. Top and bottom surfaces of each of the dielectric patterns are respectively in contact with adjacent ones of the interlayer dielectric layers.
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公开(公告)号：US10249816B2
公开(公告)日：2019-04-02
申请号：US15996605
申请日：2018-06-04
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Jong-Uk Kim , Jung-Moo Lee , Soon-Oh Park , Jung-Hwan Park , Sug-Woo Jung
Abstract: A method of manufacturing a magnetoresistive random access memory device, the method including forming a memory structure on a substrate, the memory structure including a lower electrode, a magnetic tunnel junction structure, and an upper electrode sequentially stacked; forming a first capping layer to cover a surface of the memory structure by a deposition process using a plasma under first conditions; and forming a second capping layer on the first capping layer by a deposition process using a plasma under second conditions different from the first conditions.
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公开(公告)号：US09318700B2
公开(公告)日：2016-04-19
申请号：US14740929
申请日：2015-06-16
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Zhe Wu , Jeong-Hee Park , Dong-Ho Ahn , Jung-Hwan Park , Jun-Ku Ahn , Sung-Lae Cho , Hideki Horii
CPC classification number: H01L45/06 , H01L27/2409 , H01L27/2463 , H01L45/1233 , H01L45/1253 , H01L45/141 , H01L45/144 , H01L45/1616 , H01L45/1625 , H01L45/1641 , H01L45/1666 , H01L45/1683
Abstract: In a method of manufacturing a phase change memory device, an insulating interlayer having a through opening is formed on a substrate, at least one conformal phase change material layer pattern is formed along the sides of the opening, and a plug-like phase change material pattern having a composition different from that of each conformal phase change material layer pattern is formed on the at least one conformal phase change material layer pattern as occupying a remaining portion of the opening. Energy is applied to the phase change material layer patterns to form a mixed phase change material layer pattern including elements from the conformal and plug-like phase change material layer patterns.
Abstract translation: 在相变存储装置的制造方法中，在基板上形成具有通孔的绝缘中间层，沿开口侧形成至少一个共形相变材料层图案，并且形成插塞状相变材料 具有不同于每个共形相变材料层图案的组成的图案形成在占据开口的剩余部分的至少一个共形相变材料层图案上。 将能量施加到相变材料层图案以形成包括来自保形和插塞状相变材料层图案的元件的混合相变材料层图案。
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公开(公告)号：US20220359563A1
公开(公告)日：2022-11-10
申请号：US17651633
申请日：2022-02-18
Applicant: Samsung Electronics Co., Ltd.
Inventor： Youngji Noh , Jung-Hwan Park , Kwangyoung Jung , Hyojoon Ryu , Jeehoon Han
IPC: H01L27/11582 , H01L27/11556 , H01L27/11519 , H01L27/11524 , H01L27/11526 , H01L27/11565 , H01L27/1157 , H01L27/11573 , H01L23/528
Abstract: Provided are three-dimensional semiconductor memory devices and electronic systems including the same. The device includes a substrate, stack structures each including interlayer dielectric layers and gate electrodes, which are alternately and repeatedly stacked on the substrate, vertical channel structures which penetrate the stack structures, and a separation structure, which extends in a first direction across between the stack structures. The separation structure includes first parts each having a pillar shape, which extend in a third direction perpendicular to a top surface of the substrate, and second parts, which extend between the interlayer dielectric layers from sidewalls of the first parts and which connect the first parts to each other in the first direction. The separation structure is spaced apart from the vertical channel structures in a second direction which intersects the first direction.
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Patent Agency Ranking
公开(公告)号：US20220216151A1
公开(公告)日：2022-07-07
申请号：US17537744
申请日：2021-11-30
Applicant: Samsung Electronics Co., Ltd.
Inventor： Donghwan Kim , Shinhwan Kang , Youngji Noh , Jung-Hwan Park , Sanghun Chun
IPC: H01L23/535 , H01L23/522 , H01L27/11582 , H01L27/11573
Abstract: Disclosed are three-dimensional semiconductor memory devices, electronic systems including the same, and methods of fabricating the same. The three-dimensional semiconductor memory device includes a substrate including a cell array region and an extension region, a peripheral circuit structure including peripheral transistors on the substrate, a stack structure including interlayer dielectric layers and gate electrodes that are alternately stacked on the peripheral circuit structure, contacts that penetrate the stack structure on the extension region and are electrically connected with the peripheral transistors and include a protruding part contacting a sidewall of one of the gate electrodes and a vertical part penetrating the stack structure, and dielectric patterns between the vertical part and respective sidewalls of the gate electrodes. Top and bottom surfaces of each of the dielectric patterns are respectively in contact with adjacent ones of the interlayer dielectric layers.
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公开(公告)号：US10706953B2
公开(公告)日：2020-07-07
申请号：US16215752
申请日：2018-12-11
Applicant: Samsung Electronics Co., Ltd.
Inventor： Seok-Jin Cho , Tae-Young Oh , Jung-Hwan Park
IPC: G11C29/44 , G06F11/10 , G11C11/408 , G11C11/4091 , G11C29/52
Abstract: A semiconductor memory device includes a memory cell array and an address decoder. The memory cell array includes a plurality of memory blocks, each of the plurality of memory blocks includes a plurality of dynamic memory cells coupled to word-lines and bit-lines, each of the plurality of memory blocks are divided into a plurality of row blocks by row block identity bits of a row address, and each of the of row blocks includes a plurality of sub-array blocks arranged in a first direction. The address decoder changes a physical row address of a memory cell that stores or outputs data based on a column address received with a write command or a read command.
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公开(公告)号：US10672978B2
公开(公告)日：2020-06-02
申请号：US16122056
申请日：2018-09-05
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Jung-Min Lee , Ju-Hyun Kim , Jung-Hwan Park , Se-Chung Oh , Dong-Kyu Lee , Kyung-Il Hong
Abstract: In a method of manufacturing a variable resistance memory device, an MTJ structure layer is formed on a substrate. The MTJ structure layer is etched in an etching chamber to form an MTJ structure. The substrate having the MTJ structure thereon is transferred to a deposition chamber through a transfer chamber. A protection layer covering a sidewall of the MTJ structure is formed in the deposition chamber. The etching chamber, the transfer chamber, and the deposition chamber are kept in a high vacuum state equal to or more than about 10−8 Torr.
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公开(公告)号：US11327838B2
公开(公告)日：2022-05-10
申请号：US16389080
申请日：2019-04-19
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Jung-Hwan Park , Tae-Young Oh , Hyung-Joon Chi , Kyung-Soo Ha , Hyong-Ryol Hwang
Abstract: A memory device includes: a first memory bank and a second memory bank; a control logic configured to receive a command and control an internal operation of the memory device; and an error correction code (ECC) circuit configured to retain in a latch circuit first read data read from the first memory bank in response to a first masked write (MWR) command for the first memory bank based on a latch control signal from the control logic, generate a first parity from data in which the first read data retained in the latch circuit is merged with first write data corresponding to the first MWR command in response to a first write control signal received from the control logic, and control an ECC operation to retain in the latch circuit second read data read from the second memory bank based on the latch control signal.
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公开(公告)号：US10026890B2
公开(公告)日：2018-07-17
申请号：US15177597
申请日：2016-06-09
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Jong-Uk Kim , Jung-Moo Lee , Soon-Oh Park , Jung-Hwan Park , Sug-Woo Jung
Abstract: A method of manufacturing a magnetoresistive random access memory device, the method including forming a memory structure on a substrate, the memory structure including a lower electrode, a magnetic tunnel junction structure, and an upper electrode sequentially stacked; forming a first capping layer to cover a surface of the memory structure by a deposition process using a plasma under first conditions; and forming a second capping layer on the first capping layer by a deposition process using a plasma under second conditions different from the first conditions.
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