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公开(公告)号：US20240206149A1
公开(公告)日：2024-06-20
申请号：US18541791
申请日：2023-12-15
Applicant: Samsung Electronics Co., Ltd.
Inventor： Minjun Lee , Hyoseok Kim , Yongseok Kim
IPC: H10B12/00
CPC classification number: H10B12/20
Abstract: A semiconductor device includes a source line extending in a first horizontal direction on a substrate, a channel layer extending in a vertical direction perpendicular to an upper surface of the substrate, and including a first end, a second end opposite to the first end, and a channel layer sidewall connecting the first end with the second end, the first end being disposed on the source line, a trap layer disposed on the channel layer sidewall, a gate insulating layer disposed on an outer surface of the trap layer, a word line disposed on at least one sidewall of the gate insulating layer and extending in a second horizontal direction crossing the first horizontal direction, a drain area disposed on the second end of the channel layer and including a metal or metal nitride, and a bit line disposed on the drain area and extending in the first horizontal direction.
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Patent Agency Ranking
公开(公告)号：US20230112070A1
公开(公告)日：2023-04-13
申请号：US17836228
申请日：2022-06-09
Applicant: Samsung Electronics Co., Ltd.
Inventor： Minjun Lee , Yongseok Kim , Hyuncheol Kim , Jongman Park , Dongsoo Woo , Kyunghwan Lee
Abstract: Provided is a memory device. The memory device may include a substrate, a ferroelectric field effect transistor disposed on the substrate, a first channel contacting a gate structure of the ferroelectric field effect transistor and extending in a vertical direction from the gate structure of the ferroelectric field effect transistor, a selection word line disposed at one side of the first channel, a first gate dielectric layer disposed between the first channel and the selection word line, and a cell word line disposed on top of the first channel.
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公开(公告)号：US11862220B2
公开(公告)日：2024-01-02
申请号：US17836228
申请日：2022-06-09
Applicant: Samsung Electronics Co., Ltd.
Inventor： Minjun Lee , Yongseok Kim , Hyuncheol Kim , Jongman Park , Dongsoo Woo , Kyunghwan Lee
CPC classification number: G11C11/2273 , G11C5/06 , G11C11/2255 , G11C11/2257 , G11C11/2275
Abstract: Provided is a memory device. The memory device may include a substrate, a ferroelectric field effect transistor disposed on the substrate, a first channel contacting a gate structure of the ferroelectric field effect transistor and extending in a vertical direction from the gate structure of the ferroelectric field effect transistor, a selection word line disposed at one side of the first channel, a first gate dielectric layer disposed between the first channel and the selection word line, and a cell word line disposed on top of the first channel.
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公开(公告)号：US20230354580A1
公开(公告)日：2023-11-02
申请号：US18115116
申请日：2023-02-28
Applicant: Samsung Electronics Co., Ltd.
Inventor： Minjun Lee , Kijoon Kim , Yongseok Kim
IPC: H10B12/00
Abstract: A semiconductor device includes a gate electrode on a substrate, a memory body structure extending through the gate electrode, a source layer at an end portion of the memory body structure and including germanium doped with p-type impurities, and a drain layer at another end portion of the memory body structure and including a metal or a metal alloy. The memory body structure may include a body including undoped polysilicon, a charge storage pattern on a sidewall of the body, and a blocking pattern on an outer sidewall of the charge storage pattern and contacting the gate electrode.
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公开(公告)号：US20240032303A1
公开(公告)日：2024-01-25
申请号：US18301597
申请日：2023-04-17
Applicant: Samsung Electronics Co., Ltd.
Inventor： Jongho WOO , Youngji Noh , Minjun Lee
Abstract: A three-dimensional semiconductor device includes a plate common source line, first and second word lines spaced apart from each other to at least partially define a vertical space therebetween, a channel pattern in the vertical space, a ferroelectric layer including a first portion between the channel pattern and the first word line, a second portion between the channel pattern and the second word line, and a third portion contacting the plate common source line, a bit line in the vertical space to contact the channel pattern and having a first width in a first horizontal direction, and a source line spaced apart from the bit line in the vertical space to contact the channel pattern, having a second width greater than the first width in the first horizontal direction, and having a source line contact portion inside the plate common source line.
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公开(公告)号：US20240023340A1
公开(公告)日：2024-01-18
申请号：US18222278
申请日：2023-07-14
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Suhwan LIM , Yongseok Kim , Juhyung Kim , Minjun Lee
IPC: H10B51/30 , H10B51/10 , H10B51/40 , H10B80/00 , H01L25/065 , H10B43/10 , H10B43/27 , H10B43/40 , H10B43/35 , H10B41/10 , H10B41/27 , H10B41/35 , H10B41/40
CPC classification number: H10B51/30 , H10B51/10 , H10B51/40 , H10B80/00 , H01L25/0652 , H10B43/10 , H10B43/27 , H10B43/40 , H10B43/35 , H10B41/10 , H10B41/27 , H10B41/35 , H10B41/40 , H01L2225/06506
Abstract: The present disclosure provides methods, apparatuses, and systems for operating and manufacturing a semiconductor device. In some embodiments, a semiconductor device includes a stack structure including interlayer insulating layers and gate electrodes, a channel layer disposed inside a hole penetrating through the stack structure, a data storage layer disposed between the stack structure and the channel layer, data storage patterns disposed between the data storage layer and the gate electrodes, and dielectric layers disposed between the data storage patterns and the gate electrodes. The interlayer insulating layers and the gate electrodes are alternately and repeatedly stacked in a first direction. A first material of the data storage layer is different from a second material of the data storage patterns.
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