公开(公告)号：US20240162350A1

公开(公告)日：2024-05-16

申请号：US18496353

申请日：2023-10-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Moonil JUNG ,  Sangwook KIM ,  Euntae KIM ,  Jeeeun YANG ,  Kwanghee LEE ,  Youngkwan CHA

IPC: H01L29/786 ,  H01L29/10 ,  H01L29/66

CPC classification number: H01L29/7869 ,  H01L29/1054 ,  H01L29/66969 ,  H01L29/78648 ,  H01L29/78696

Abstract: Semiconductor devices and manufacturing methods thereof are provided. A semiconductor device includes a substrate, a lower electrode on the substrate, an oxide channel on the lower electrode, the oxide channel including vertical extension portions extending in a first direction perpendicular to the substrate, an upper electrode on the oxide channel, a gate insulator on a portion the oxide channel that is exposed by the lower electrode and the upper electrode, and a gate electrode on the gate insulator, wherein the upper electrode and the lower electrode are separated from each other by the oxide channel in the first direction, and the oxide channel is doped with ions.

公开(公告)号：US20250006844A1

公开(公告)日：2025-01-02

申请号：US18756169

申请日：2024-06-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jeeeun YANG ,  Sangwook KIM ,  Youngkwan CHA

IPC: H01L29/786 ,  H01L27/118 ,  H01L29/66 ,  H10B10/00

Abstract: A semiconductor device includes an oxide semiconductor layer, a first electrode and a second electrode, which are arranged apart from each other on the oxide semiconductor layer, a metal oxide layer arranged between the oxide semiconductor layer and at least one of the first electrode and the second electrode, and a metal nitride layer arranged between the metal oxide layer and the oxide semiconductor layer.

公开(公告)号：US20240215215A1

公开(公告)日：2024-06-27

申请号：US18534220

申请日：2023-12-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sangwook KIM ,  Kwanghee LEE ,  Jeeeun YANG ,  Moonil JUNG ,  Euntae KIM ,  Youngkwan CHA

IPC: H10B12/00

CPC classification number: H10B12/00

Abstract: A memory device includes a read word line on a substrate, a first channel extending along a plane perpendicular to an upper surface of the substrate, a second channel facing the first channel in parallel, a first gate insulation layer adjacent to the first channel between the first channel and the second channel, a second gate insulation layer adjacent to the second channel between the first channel and the second channel, a gate electrode adjacent to the first gate insulation layer between the first gate insulation layer and the second gate insulation layer, a write word line adjacent to the second gate insulation layer between the first gate insulation layer and the second gate insulation layer, a read bit line electrically connected to the first channel, and a write bit line electrically connected to the second channel.

公开(公告)号：US20230040335A1

公开(公告)日：2023-02-09

申请号：US17716460

申请日：2022-04-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaechul PARK ,  Youngkwan CHA

IPC: H01L29/78 ,  H01L29/51 ,  H01L27/1159

Abstract: A semiconductor device includes a semiconductor layer extending in a first direction and including a source region and a drain region, which are apart from each other in the first direction; an insulating layer surrounding the semiconductor layer; a first gate electrode layer surrounding the insulating layer; a ferroelectric layer provided on the first gate electrode layer; and a second gate electrode layer provided on the ferroelectric layer.

公开(公告)号：US20220285401A1

公开(公告)日：2022-09-08

申请号：US17688043

申请日：2022-03-07

Applicant: Samsung Electronics Co., Ltd. ,  KOREA ADVANCED INSTITUTE OF SCIENCE AND TECHNOLOGY

Inventor： Youngkwan CHA ,  Jaechul PARK ,  Sanghun JEON

IPC: H01L27/11597 ,  H01L27/11587

Abstract: Provided are semiconductor devices having a three-dimensional stacked structure and methods of manufacturing the same. A semiconductor device includes a plurality of channel structures on a substrate and arranged in a three-dimensional array; a plurality of gate electrodes extending in a direction parallel to the substrate; and a plurality of source and drain electrodes extending in a direction perpendicular to the substrate. The gate electrodes are connected to the channel structures arranged in the direction parallel to the substrate, and the source and drain electrodes are connected to the channel structures arranged in the direction perpendicular to the substrate. The channel structures include a channel layer and a ferroelectric layer on the channel layer.